Embedded Via Interconnect Layout for Lower Contact Resistance
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Solution Overview
Problem
Conventional semiconductor interconnects face high resistance due to poor cross-plane conductivity and challenging contact resistance between line conductors and vias, particularly with anisotropic and topological conductors.
Innovation Solution
Incorporating anisotropic materials with aligned high conductivity orientations in conductive lines and embedding vias transversely within these lines to enhance electrical contact, using methods like reactive ion etching and deposition of isotropic metals to form embedded vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional via structures are used, then manufacturing is simpler, but resistance between line conductor and via is poor
Solution Approach 1:
The first via portion is formed to extend into the anisotropic conductor before the conductor is fully encapsulated in dielectric material. This preliminary action ensures optimal electrical contact is established with the high-conductivity anisotropic material before subsequent processing steps, improving resistance without requiring complex post-fabrication modifications
Solution Approach 2:
The via structure is nested within the conductive line geometry, with the first via portion embedded in the anisotropic conductor and the second via portion extending outward. This nested configuration allows the via to be integrated into the interconnect architecture while maintaining both manufacturing feasibility and electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces line and contact resistance by channeling electric current flow horizontally and vertically, improving connectivity and conductivity in semiconductor devices.
Implementation Method 1
anisotropic materials with aligned high conductivity orientations in conductive lines
Implementation Method 2
An embedded via is transversely oriented relative to the longitudinal direction. The embedded via is disposed within and in electrical contact with internal surfaces of the conductive line
Data Source
AI summary
A semiconductor device includes a conductive line including an anisotropic material having crystal orientations of higher conductivity aligned parallel with a longitudinal direction of the conductive line. An embedded via is transversely oriented relative to the longitudinal direction. The embedded via is disposed within and in electrical contact with internal surfaces of the conductive line. A via is connected to the embedded via.