Embedded Via Pad Design for High-Density PCB Interconnects
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Solution Overview
Problem
Existing printed circuit board manufacturing methods face limitations in reducing via size while maintaining a uniform aspect ratio, leading to difficulties in achieving high-density interlayer connections and fine circuits due to increased aspect ratios and limitations in substrate types and plating processes.
Innovation Solution
A printed circuit board design where a portion of the pad is embedded in the insulator, and the via is formed under an opening in the insulator, allowing for reduced via height without increasing the aspect ratio, using a method that includes forming openings with laser processing and filling with metal through electroless plating or other techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the via is reduced to achieve high-density interlayer connection, then the density of interlayer connection is improved, but the aspect ratio of the via increases making plating and processing difficult
Solution Approach 1:
The via structure is segmented into two parts: an upper via portion and a lower via portion with different diameters. The upper via has a larger diameter for easy plating, while the lower via has a smaller diameter for high-density connection. This segmentation allows each portion to be optimized independently, resolving the contradiction between via size reduction and plating difficulty.
Solution Approach 2:
Different portions of the via have different local qualities (diameters). The upper portion has a larger diameter suitable for plating operations, while the lower portion has a smaller diameter for achieving high-density connections. This local variation in quality allows the via to satisfy both plating requirements and density requirements simultaneously.
2Manufacturing precision
If a thin insulator is used to maintain uniform aspect ratio, then the aspect ratio uniformity is improved, but the type of available substrates is limited
Solution Approach 1:
The via structure is divided into upper and lower portions with different diameters, allowing the via to be formed in a standard-thickness insulator while maintaining uniform aspect ratio. This segmentation eliminates the need to use thin insulators, thereby expanding substrate type availability while preserving aspect ratio uniformity.
Solution Approach 2:
The via diameter parameter is changed along the vertical direction, with the upper portion having a larger diameter and the lower portion having a smaller diameter. This parameter change allows the via to be formed in insulators of standard thickness while maintaining uniform aspect ratio, thus expanding substrate compatibility.
3Manufacturing precision
If the size of the via is reduced, then the via size is improved, but the plating process becomes unstable with increased defects
Solution Approach 1:
The via plating process is segmented into two stages corresponding to the two via portions. The upper via portion with larger diameter is plated first with stable plating, followed by the lower via portion with smaller diameter. This segmentation allows each plating operation to be performed under optimal conditions, reducing defects and improving overall plating stability.
Solution Approach 2:
The upper via portion is plated before the lower via portion. This preliminary action ensures that the larger-diameter upper portion is filled with metal first, providing a stable foundation and reducing the risk of plating defects in the subsequent smaller-diameter lower portion plating operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of via size while maintaining a uniform aspect ratio, minimizing plating defects and stabilizing the plating process, allowing for high-density interlayer connections and fine circuits with reduced manufacturing costs and complexity.
Implementation Method 1
forming openings with laser processing
Implementation Method 2
filling with metal through electroless plating or other techniques
Data Source
AI summary
The present invention relates to a printed circuit board including: a first circuit pattern formed on a first insulator; a second insulator formed on the first insulator; a second circuit pattern having a pad of which a portion is embedded in the second insulator and a via which penetrates the second insulator to electrically connect the first circuit pattern and the pad; and a third circuit pattern formed on the second insulator, and it is possible to reduce a size of the via without increasing an aspect ratio.