Embedded Wafer-Level Package I/O Redesign
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Solution Overview
Problem
As semiconductor dies become smaller and more functional, conventional packaging technologies face challenges in increasing I/O pad density and efficiency, leading to limitations in fan-in packages and potential solder bridges due to fixed pad pitch and ball size constraints.
Innovation Solution
The development of an embedded wafer-level package structure that includes metal pillars and a redistribution layer, allowing for fan-out packaging by redistributing I/O pads to a larger area, and using a molding compound to surround the dies, which enables increased I/O pad density and reduces packaging complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fan-in packaging is used to maintain high throughput and lower cost, then packaging efficiency is improved, but I/O pad density is limited due to fixed pad pitch and ball size constraints
Solution Approach 1:
The patent transitions from fan-in packaging (where I/O pads are confined to the die surface area) to fan-out packaging (where I/O pads are redistributed to a larger area). This dimensional expansion allows the same number of I/O pads to be accommodated on a larger footprint, effectively increasing I/O pad density while maintaining packaging efficiency.
Solution Approach 2:
The patent segments the packaging process into distinct stages: die attachment to carrier, molding compound application, carrier removal, and I/O pad redistribution. This segmentation enables the I/O pads to be redistributed after the die is attached, allowing for higher I/O pad density without compromising the initial packaging efficiency.
2Quantity of substance
If I/O pad pitch is decreased to increase I/O pad density, then I/O pad density is improved, but solder bridges may occur
Solution Approach 1:
By redistributing I/O pads to a larger area through fan-out packaging, the patent increases the effective pitch between adjacent I/O pads. This dimensional expansion reduces the risk of solder bridges while still achieving high I/O pad density, as the pads are spread out over a greater surface area.
Solution Approach 2:
The patent performs I/O pad redistribution after the die is attached to the carrier but before final packaging completion. This preliminary action allows for optimized I/O pad spacing that prevents solder bridges while maintaining high density, as the redistribution is planned and executed before the actual soldering process.
3Reliability
If only known-good-dies are packaged after sawing to improve reliability, then defect rate is reduced, but packaging complexity increases
Solution Approach 1:
The patent performs die attachment to carrier before the sawing process. This preliminary action allows all dies on the wafer to be packaged together in one batch, rather than requiring individual die inspection and packaging. The subsequent sawing process separates the packaged dies without affecting the already-attached configuration, thereby maintaining reliability while reducing packaging complexity.
Solution Approach 2:
The patent merges the die attachment process with the wafer-level processing by attaching multiple dies to a carrier before sawing. This combining of operations allows for batch processing of multiple dies, reducing the overall packaging complexity compared to individual die handling, while maintaining high reliability through the embedded wafer-level bonding approach.
Data Source
AI summary
A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.