Embedded Wiring Board Layout for Lower Resistance Loss
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Solution Overview
Problem
Existing wiring boards with embedded electronic components face challenges in minimizing resistance loss, which affects power supply efficiency and stability.
Innovation Solution
The wiring board design incorporates a first interconnect structure with a high-density second interconnect layer, a first insulating layer with a through hole for embedding an electronic component, and an embedding resin that covers the component and fills the gap between insulating layers, reducing electrical path length and resistance loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If an electronic component is embedded in a through hole of the first insulating layer, then the board can accommodate electronic components without increasing size, but resistance loss increases due to longer electrical paths
Solution Approach 1:
The patent transitions from planar interconnect routing to three-dimensional vertical routing through the first insulating layer. The second interconnect layer is positioned at a different vertical dimension (below the first insulating layer) to create a shorter electrical path, reducing resistance loss while maintaining compact board area.
Solution Approach 2:
The electronic component is embedded within the through hole of the first insulating layer, with the second interconnect layer nested below it. This nested configuration allows multiple functional elements (component, interconnect layers, insulating layers) to occupy overlapping spatial volumes, minimizing board area while managing electrical paths.
2Loss of energy
If a high-density interconnect layer is added to reduce resistance loss, then electrical performance improves, but device complexity increases
Solution Approach 1:
The interconnect structure is segmented into multiple distinct layers (first interconnect layer, second interconnect layer) separated by insulating layers. Each layer serves a specific routing function, allowing independent optimization of interconnect density and trace routing to reduce resistance loss while managing complexity through functional separation.
Solution Approach 2:
The patent adds vertical dimensionality by positioning the second interconnect layer below the first insulating layer, creating a three-dimensional interconnect architecture. This vertical stacking reduces horizontal routing length and resistance loss without significantly increasing lateral device complexity.
Data Source
AI summary
A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure, and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure. The second interconnect layer has an interconnect density higher than those of the first and the third interconnect layers. The first insulating layer has a through hole penetrating the first insulating layer, and an electronic component electrically connected to the second interconnect layer is disposed inside the through hole. An embedding resin covering the electronic component is provided inside the through hole, and extends to cover the first insulating layer and fills in between the first and second insulating layers.