Embedded Wiring Substrate Layout for Fine-Pitch Insulation Reliability
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Solution Overview
Problem
Existing wiring substrates with fine patterns are prone to short circuits due to close inter-wiring distances and exposure of filler particles, leading to defects in signal transmission.
Innovation Solution
A wiring substrate design with an insulating layer containing filler particles and an embedded wiring layer, where the inter-wiring distance is between 2 μm to 8 μm and the maximum filler particle size is 50% or less of the inter-wiring distance, along with a manufacturing process that includes forming grooves and covering them with a metal film layer to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the inter-wiring distance is reduced to increase wiring density, then the number of wirings per unit area increases, but the risk of short circuits increases due to exposure of filler particles
Solution Approach 1:
The patent changes the parameter of filler particle size relative to inter-wiring distance. Specifically, it stipulates that the maximum particle size of filler particles should be 50% or less of the inter-wiring distance, allowing high wiring density while preventing short circuits by ensuring filler particles do not expose between adjacent wirings
Solution Approach 2:
The patent uses a composite insulating layer structure combining resin and filler particles with controlled size distribution. This composite material approach allows the insulating layer to maintain both high density (supporting close wiring) and high reliability (preventing filler exposure and short circuits)
2Manufacturing precision
If the inter-wiring distance is reduced to achieve fine patterns, then the wiring substrate can support higher integration, but defects in signal transmission occur due to short circuits
Solution Approach 1:
The patent establishes a specific parameter relationship where maximum filler particle size ≤ 50% of inter-wiring distance. This parameter control enables fine patterns with small inter-wiring distances (2-8 μm) while preventing filler particle exposure that would cause signal transmission defects
Solution Approach 2:
The patent applies preliminary action by pre-controlling the filler particle size distribution before wiring formation. By ensuring filler particles are sufficiently small relative to the intended inter-wiring distance, the design prevents future short circuit issues in fine pattern applications
3Reliability
If larger filler particles are used to improve insulating properties, then the insulation performance increases, but the maximum particle size exceeds 50% of inter-wiring distance causing short circuit risks
Solution Approach 1:
The patent optimizes the parameter of filler particle size by setting it to maximum 50% of inter-wiring distance. This balanced parameter selection maintains good insulation performance while preventing particle exposure between closely spaced wirings, resolving the contradiction between insulation performance and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design and manufacturing method enhance insulation reliability and reduce the risk of short circuits, ensuring high-frequency signal transmission with improved symmetry and reduced warpage.
Implementation Method 1
forming a metal film layer covering the inner surfaces of the grooves
Implementation Method 2
forming a plating film layer on the metal film layer
Data Source
AI summary
A wiring substrate includes an insulating layer including resin and filler particles, and an embedded wiring layer including wirings and embedded in the insulating layer such that the wirings are filling grooves formed on a surface of the insulating layer, respectively. The embedded wiring layer is formed such that the inter-wiring distance between the closest two wirings of the wirings in the embedded wiring layer is in the range of 2 μm to 8 μm, and the insulating layer is formed such that the maximum particle size of the filler particles is 50% or less of the inter-wiring distance.