Embedded Wiring Layer Circuit Board Void Prevention
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Solution Overview
Problem
Existing circuit boards incorporating semiconductor ICs face inefficiencies in wiring layer use due to voids generated between the die attach material and insulating layers, leading to reduced reliability and limited functionality.
Innovation Solution
A circuit board design where the first wiring layer is embedded within the first insulating layer, ensuring both surfaces are coplanar, allowing the die attach material to contact both layers without voids, and enabling additional wiring layers to be formed for increased efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a wiring layer is formed on an insulating layer before mounting the semiconductor IC, then the wiring structure can be established early in the manufacturing process, but voids are generated between the die attach material and insulating layer due to level differences, reducing reliability
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by first mounting the semiconductor IC on the insulating layer, then forming the wiring layer on top of the mounted IC. This reversal eliminates the level difference problem that causes voids, as the wiring layer is now formed on a flat surface created by the IC mounting process rather than attempting to cover pre-formed wiring structures.
Solution Approach 2:
The patent performs the IC mounting action before forming the wiring layer, establishing the final surface level in advance. This preliminary action creates a flat reference surface that eliminates subsequent void formation issues when the wiring layer is deposited, ensuring complete contact between the die attach material and insulating layer.
2Productivity
If the wiring layer is formed on the insulating layer surface, then the wiring structure can be created, but the bottom surface of the semiconductor IC cannot be utilized for wiring, reducing wiring layer use efficiency
Solution Approach 1:
The patent utilizes the bottom surface of the semiconductor IC as an additional wiring dimension. By forming a wiring layer on the bottom surface of the IC (facing the insulating layer) and another wiring layer on the top surface, the patent effectively adds a third dimension to the wiring structure, dramatically increasing wiring layer use efficiency without proportionally increasing overall device complexity.
Data Source
AI summary
Disclosed herein is a circuit board that includes a first insulating layer having an upper surface; a first wiring layer embedded in the first insulating layer, the first wiring layer having an upper surface exposed from the upper surface of the first insulating layer such that the upper surface of the first wiring layer is substantially coplanar with the upper surface of the first insulating layer; a semiconductor IC mounted on the upper surface of the first wiring layer with a die attach material interposed therebetween; and a second insulating layer stacked on the upper surface of the first wiring layer so as to embed the semiconductor IC, wherein a bottom surface of the die attach material is in contact with both of the upper surface of the first insulating layer and the upper surface of the first wiring layer.