Embedded Wiring Layer Structure to Prevent Conductor Oxidation

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving miniaturization, low power consumption, high reliability, low off-state current, long data retention, and eye-friendliness, particularly in display devices, where existing materials and manufacturing methods struggle to optimize these features simultaneously.

Innovation Solution

A method for manufacturing a wiring layer involves forming insulators and conductors in a specific sequence, with polishing treatments to ensure the conductors are embedded within the insulators, preventing oxygen penetration and oxidation, which enhances the semiconductor device's performance by reducing off-state current and improving data retention while allowing for miniaturization and transparency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional wiring layer manufacturing methods are used, then manufacturing simplicity is maintained, but oxygen penetration and oxidation occur leading to increased off-state current and reduced reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the wiring layer into multiple layers (first wiring layer, second wiring layer, third wiring layer) with insulating films between them. This segmentation allows each layer to be independently controlled and protected from oxygen penetration, preventing oxidation while maintaining manufacturing feasibility through systematic process design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent embeds conductors within insulators in a nested structure where the first conductor is surrounded by the first insulator, the second conductor by the second insulator, and the third conductor by the third insulator. This nested configuration physically prevents oxygen from reaching the conductors, eliminating oxidation issues while integrating multiple functional layers.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Loss of energy

If conductor surfaces are exposed, then manufacturing is simpler, but oxidation occurs increasing off-state current and reducing data retention

Engineering Contradiction:
Improveoff-state currentVSAvoidwiring layer manufacturing ease
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The patent applies preliminary protective action by forming insulating films over the conductors before subsequent processing steps. The first insulator is formed over the first conductor, followed by the second insulator over the second conductor, and the third insulator over the third conductor. This preliminary insulation prevents oxidation during manufacturing and operation, reducing off-state current while maintaining ease of manufacture through standardized film formation processes.

Inventive Principle:
Principle #10Preliminary action

3Area of moving object

If device size is reduced for miniaturization, then integration density increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice areaVSAvoidwiring layer precision
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by forming insulating films with specific properties at different locations. The first insulator has different characteristics from the second and third insulators, allowing optimized protection for each conductor layer. This localized approach enables precise control of oxygen barrier properties and electrical characteristics in miniaturized structures without compromising manufacturing precision.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent transitions from planar wiring to a three-dimensional stacked configuration with conductors at different vertical levels. The first, second, and third conductors are arranged in multiple layers separated by insulators, utilizing the vertical dimension to achieve miniaturization while maintaining adequate spacing and protection for each conductor, thereby reducing manufacturing precision requirements in the lateral direction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Use of energy by moving object

If oxide semiconductors are used for low power consumption, then energy efficiency improves, but transparency and eye-friendliness require additional optimization

Engineering Contradiction:
Improvepower consumptionVSAvoiddisplay brightness and eye-friendliness
Core Design Contradiction:
Use of energy by moving objectVSIllumination intensity

Solution Approach 1:

The patent employs composite material structures combining oxide semiconductor layers with specific insulating materials. The insulators are configured to provide both electrical isolation and optical properties that enhance transparency. This composite approach maintains the low power consumption characteristics of oxide semiconductors while optimizing light transmission for eye-friendly display performance.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in a miniaturized semiconductor device with low power consumption, high reliability, and the ability to retain data for a long period, while also enabling the creation of eye-friendly display devices with transparent semiconductors, addressing the limitations of existing technologies.

Implementation Method 1

An oxide semiconductor can be deposited by a sputtering method or the like

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 2

performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator

Methodology Applied
Scientific EffectMechanical polishing: Abrasion

Data Source

PatentUS11901372B2Wiring layer and manufacturing method therefor
Publication Date: 2024.02.13 SEMICON ENERGY LAB CO LTD
  • US11901372B2 patent drawing
  • US11901372B2 patent drawing
  • US11901372B2 patent drawing

AI summary

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.