Embedded Wiring Post in RDL Pad for Semiconductor Package Stability

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Solution Overview

Problem

Semiconductor packages face challenges in achieving structural stability between wiring posts and pads, particularly in miniaturized designs where thickness is decreasing while functionality and capacity are increasing, leading to potential reliability issues.

Innovation Solution

The solution involves disposing at least a part of the wiring post inside a recess formed in the wiring pad within a redistribution layer, enhancing structural stability by using a metal seed layer on the recess's sidewalls and bottom surface, and a solder resist layer with conductive terminals and solder balls for electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the thickness of semiconductor packages is decreased to meet demand for thin electronic devices, then the package becomes thinner and more compact, but the structural stability between wiring post and wiring pad deteriorates

Engineering Contradiction:
Improvethickness of semiconductor packageVSAvoidstructural stability between wiring post and wiring pad
Core Design Contradiction:
Length of stationary objectVSStability of the object's composition

Solution Approach 1:

The wiring post is disposed inside a recess formed in the wiring pad, creating a nested structure where one component is embedded within another. This nesting arrangement enhances the structural stability between the wiring post and wiring pad while maintaining a thin package profile, as the wiring post integrates into the pad structure rather than extending outward.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

Instead of increasing the horizontal size of the wiring pad to improve stability, the solution moves to the vertical dimension by forming a recess into the pad and embedding the wiring post within it. This dimensional transition allows stability enhancement without increasing the overall package footprint or thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple semiconductor chips are incorporated into a single package to achieve high capacity and multi-functionality, then the functional capacity increases, but the device complexity increases

Engineering Contradiction:
Improvemulti-functionality and high capacityVSAvoidcomplexity of incorporating multiple chips
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Multiple semiconductor chips are incorporated into a single package substrate, merging multiple functional components into one integrated structure. The common wiring pad structure with recesses for wiring posts provides a unified approach to connecting multiple chips, reducing the overall system complexity compared to separate packages.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The wiring pad structure with recesses serves multiple functions: it provides electrical connection points, structural support, and mechanical anchoring for wiring posts from different semiconductor chips. This universal structure simplifies the design by using the same configuration for multiple chip connections rather than requiring different structures for each chip.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230134201A1Semiconductor package
Publication Date: 2023.05.04 SAMSUNG ELECTRONICS CO LTD
  • US20230134201A1 patent drawing
  • US20230134201A1 patent drawing
  • US20230134201A1 patent drawing

AI summary

A semiconductor package includes a substrate including a first wiring pattern, a redistribution layer disposed on an upper surface of the substrate, a solder resist layer disposed on an upper surface of the redistribution layer and including a second recess formed inside the solder resist layer, a first conductive terminal disposed on sidewalls and a bottom surface of the second recess, a first solder ball disposed on the first conductive terminal, and a semiconductor chip disposed on the solder resist layer and electrically directly connected to the redistribution layer through the first solder ball. The redistribution layer includes a first wiring pad, a first recess formed on an upper surface of the first wiring pad, a first metal seed layer disposed on sidewalls and a bottom surface of the first recess, and a first wiring post at least partially disposed on the first metal seed layer inside the first recess.