Embedded Wiring on RDL Bumps for Thin High-Current Packages
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Solution Overview
Problem
Conventional semiconductor packages are thick due to the presence of a substrate, and limitations in photoresist patterning restrict the electrical current that can reach the die, making them unsuitable for high-power applications.
Innovation Solution
The development of semiconductor packages with embedded wiring on re-distributed bumps, which use a temporary carrier instead of a substrate, allowing for multiple re-distribution layer (RDL) stacking and thicker wire bonds to accommodate higher electrical current inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a substrate is used in conventional semiconductor packages, then structural support is provided, but the package thickness increases
Solution Approach 1:
The patent removes the substrate from the semiconductor package structure, extracting the problematic element that caused increased thickness. The package is reconfigured to use the carrier as the primary structural support, eliminating the need for a separate substrate layer and thereby reducing overall package thickness while maintaining structural integrity.
Solution Approach 2:
The patent transitions from a traditional planar substrate-based architecture to a vertical stacking architecture where multiple RDL layers are stacked above the carrier. This dimensional reorganization allows the package to achieve its structural function without the thickness penalty of a substrate, utilizing the vertical dimension for RDL stacking instead.
2Power
If photoresist patterning is used with a substrate, then wiring patterns are formed, but electrical current capacity is restricted
Solution Approach 1:
The patent introduces a carrier as an intermediary structure that replaces the substrate's patterning function. The carrier provides a platform for forming RDL layers with thicker wire bonds that can accommodate higher electrical current inputs, bypassing the current restrictions imposed by photoresist patterning on substrates while still enabling precise wiring pattern formation.
Solution Approach 2:
The patent changes the physical parameters of the wiring structure by using thicker wire bonds in the RDL layers formed on the carrier. This parameter change increases the electrical current capacity compared to the thin traces limited by photoresist patterning, while the carrier's surface properties enable effective adhesion and patterning of these thicker conductors.
3Length of moving object
If multiple RDL layers are stacked without a substrate, then package thickness is reduced, but structural support becomes challenging
Solution Approach 1:
The patent makes the carrier multi-functional, serving both as the structural support traditionally provided by a substrate and as the foundation for RDL stacking. The carrier performs dual roles: providing mechanical strength and structural integrity while also enabling the formation and support of multiple thin RDL layers, thereby resolving the conflict between reduced thickness and maintained strength.
Solution Approach 2:
The patent employs a composite structure combining the carrier with multiple RDL layers, each comprising conductive traces, dielectric materials, and solder bumps. This composite architecture distributes mechanical loads across multiple layers and interfaces, providing adequate structural support despite the reduced overall thickness achieved by eliminating the substrate.
4Ease of manufacture
If heterogeneous integration and embedded stack chips are used, then costs are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by attaching multiple different semiconductor chips to the carrier in predetermined positions before forming the RDL layers. This preliminary chip attachment enables subsequent RDL routing to efficiently interconnect heterogeneous devices, simplifying the overall manufacturing process despite the complexity of integrating different chip types, and reducing costs through early optimization of the interconnection architecture.
Data Source
AI summary
Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.