Embedded WLP Die in PCB Cavity for Compact Electrical Module
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Solution Overview
Problem
Existing electrical module assemblies with stacked printed circuit boards face issues such as defective monolithic microwave integrated circuit (MMIC) dies causing malfunctions, coarse design rules leading to poor performance, and high manufacturing costs due to embedding MMIC dies in the core layer of PCBs.
Innovation Solution
The implementation of wafer-level packaging for fully-tested MMIC dies, forming cavities in build-up layers of PCBs, and embedding wafer-level packaged (WLP) dies within these cavities, allowing for finer design rules, compact routing, and concurrent PCB and MMIC fabrication, reducing manufacturing costs and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MMIC dies are embedded in the core layer of PCB, then the electrical module assembly can be manufactured, but the manufacturing cost increases significantly
Solution Approach 1:
The patent extracts the MMIC die embedding process from the core layer and relocates it to the build-up layers. This extraction allows the use of pre-tested known-good dies (KGDs) that are wafer-level packaged, eliminating the need for expensive core layer embedding while maintaining electrical performance. The build-up layers provide a more cost-effective substrate for die integration.
Solution Approach 2:
The patent applies preliminary action by testing and packaging MMIC dies at the wafer level before embedding them in the PCB. This preliminary testing ensures that only known-good dies are selected and packaged, eliminating defective dies before they reach the PCB assembly stage. This approach reduces rework costs and improves yield while lowering overall manufacturing costs.
2Ease of manufacture
If MMIC dies are embedded in the core layer of PCB, then the assembly can be constructed, but the design rules become coarse and process variations increase
Solution Approach 1:
The patent extracts the die embedding location from the core layer to the build-up layers, where finer design rules and tighter process control are available. This relocation enables more precise electrical routing and better control over manufacturing variations, improving overall assembly precision.
Solution Approach 2:
The patent applies local quality by using different PCB layers with different characteristics - the build-up layers provide finer design rules and tighter tolerances for die embedding, while the core layer maintains its structural role. This localized optimization allows precise die placement without compromising the overall PCB structure.
3Ease of manufacture
If MMIC dies are embedded in the core layer of PCB, then the electrical module can be assembled, but one defective die may cause malfunction of the whole PCB
Solution Approach 1:
The patent applies preliminary action by testing and packaging MMIC dies at the wafer level before embedding them in the PCB. This preliminary testing ensures that only known-good dies are selected and packaged, eliminating defective dies before they reach the PCB assembly stage. This approach reduces rework costs and improves yield while lowering overall manufacturing costs.
Solution Approach 2:
The patent provides beforehand cushioning by implementing a selection and packaging process that identifies and isolates defective dies before they can cause system failure. The wafer-level packaging with pre-testing creates a buffer that protects the final assembly from defects, ensuring higher reliability.
4Ease of manufacture
If coarse design rules are used in PCB, then the manufacturing is simpler, but the electrical routing becomes longer and more complicated
Solution Approach 1:
The patent extracts the die embedding location from the core layer to the build-up layers, where finer design rules and tighter process control are available. This relocation enables more precise electrical routing and better control over manufacturing variations, improving overall assembly precision.
Data Source
AI summary
An electrical module assembly is provided. The electrical module assembly includes a circuit board with a first circuit-board surface and a second circuit-board surface defining a cavity, and an antenna disposed on the first circuit-board surface. The electrical module assembly also includes a wafer-level packaged (WLP) die embedded in the cavity. The WLP die has a first WLP die surface and a second WLP die surface. The second WLP die surface has electrical contacts thereon. The circuit board includes vias that extend from the antenna through the circuit board to the first WLP die surface to interconnect the antenna and the WLP die. The electrical module assembly further includes a second circuit board coupled to the second circuit-board surface, and coupled to the WLP die at the electrical contacts on the second WLP die surface of the WLP die.