Embedding 3D Lattice Structures in Analog Processors
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Solution Overview
Problem
Current analog processors are limited in processing problems with size and connectivity that exceed their physical topology, requiring more computation devices and couplers than they provide, making it difficult to simulate three-dimensional structures effectively.
Innovation Solution
A system is developed where a three-dimensional structure is embedded within a plurality of cells, each with sets of qubits and couplers, forming logical qubits with ferromagnetic and tunable coupling strengths to simulate a three-dimensional lattice, allowing for the creation of a cubic lattice within the analog processor's working graph.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the analog processor uses its physical topology directly for computation, then the device complexity is low, but the problem size and connectivity that can be processed are limited
Solution Approach 1:
The patent divides the problem graph into multiple smaller problem graphs that can be processed by individual cells in the analog processor. Each cell handles a subset of the total problem, allowing the system to scale to larger problem sizes without proportionally increasing the complexity of each computational unit. This segmentation enables processing of problems exceeding the processor's physical topology constraints.
Solution Approach 2:
The patent implements a hierarchical structure where multiple levels of problem graphs are nested within each other. Problem graphs at different hierarchical levels are embedded within cells and supercells, allowing the system to represent and process large-scale problems by nesting smaller computational units within larger organizational structures. This nesting approach enables the analog processor to handle problem sizes that exceed its physical topology while maintaining manageable device complexity at each level.
2Quantity of substance
If more computation devices and couplers are added to increase problem size capacity, then the problem size that can be processed increases, but the device complexity increases
Solution Approach 1:
The patent designs cells and supercells to serve multiple functions: they act as both computational units for their local problem graphs and as organizational structures for hierarchical nesting. Each cell can independently process a small problem graph while simultaneously serving as a building block for larger supercell structures. This multi-functionality allows the system to scale problem size capacity without proportionally increasing overall device complexity, as the same structural elements serve multiple purposes at different hierarchical levels.
3Adaptability or versatility
If the analog processor attempts to process problems with connectivity exceeding its working graph, then the problem connectivity that can be handled increases, but the measurement precision deteriorates due to degeneracy
Solution Approach 1:
The patent introduces a hierarchical dimension to the analog processor's working graph by organizing cells into supercells and establishing connectivity across multiple hierarchical levels. This additional hierarchical dimension allows the system to handle problems with connectivity patterns that exceed the original two-dimensional cell layout, as connections can now traverse multiple levels of the hierarchy. The hierarchical structure provides new pathways for information flow that mitigate degeneracy effects while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simulation of complex three-dimensional structures, mitigating degeneracy effects and allowing for the computation of problem graphs that exceed the working graph of the analog processor, enhancing computational capabilities and susceptibility measurements.
Implementation Method 1
Each logical qubit respectively comprising: at least one qubit in the first set of qubits of a first cell of the respective set of cells, at least one qubit in the second set of qubits in the first cell of the respective set of cells, communicatively coupled to the at least one qubit in the first set of qubits of the first cell of the respective set of cells;
Data Source
AI summary
A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.