EMFI Detection Circuit Using Dual-Sensitivity Logic Nodes

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Solution Overview

Problem

Current technologies lack effective methods to detect and defend against electromagnetic fault injection (EMFI) attacks on digital systems.

Innovation Solution

Implementing an EMFI detector with first and second driving circuitry, where the second node is made more sensitive to EM pulses than the first, and comparing their logic states to detect anomalies, using techniques such as slower slew rate clocks, weaker power headers, lower supply voltages, or longer FET channels to enhance sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional digital circuitry is used without special detection mechanisms, then the system operates with standard performance and complexity, but it becomes vulnerable to EMFI attacks that can induce unpredictable faults

Engineering Contradiction:
Improveresistance to EMFI attacksVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The digital circuit is divided into two separate logic paths: a primary path using standard circuitry and a secondary path using EM-sensitive circuitry. This segmentation allows the system to maintain normal operation while simultaneously detecting EMFI attacks through comparison of the two paths' outputs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An intermediary comparison mechanism is introduced that takes outputs from both the primary and secondary logic paths and determines whether they match. This intermediary component enables attack detection without requiring complete redesign of the entire digital system.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If EM-sensitive nodes are created using slower slew rate clocks, weaker power headers, lower supply voltages, or longer FET channels, then the detector becomes more sensitive to EM pulses, but the circuit complexity and design difficulty increase

Engineering Contradiction:
Improvesensitivity to EM pulsesVSAvoidcircuit design
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The secondary logic path uses modified physical parameters including slower clock slew rates, weaker power headers, lower supply voltages, or longer FET channel lengths to create EM-sensitive nodes. These parameter changes make the secondary path more susceptible to EM pulses while maintaining functional equivalence to the primary path under normal conditions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The EMFI detector effectively identifies EMFI attacks by detecting unexpected logic state changes, allowing the system to take defensive actions, thereby enhancing security against such attacks.

Implementation Method 1

an electromagnetic signal such as a pulse is applied in close proximity to a target circuit or to one or more components of a target electronic system

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS12443760B2Detection of electromagnetic fault injection attacks on digital systems
Publication Date: 2025.10.14 NVIDIA CORP
  • US12443760B2 patent drawing
  • US12443760B2 patent drawing
  • US12443760B2 patent drawing

AI summary

Techniques are described for detecting an electromagnetic (“EM”) fault injection attack directed toward circuitry in a target digital system. In various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. The driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an EM pulse than has a logic state on the first node. Comparison circuitry may be coupled to the first and to the second nodes to assert an attack detection output responsive to sensing a logic state on the second node that is unexpected relative to a logic state on the first node.