Embedded Semiconductor Package EMI Mitigation via Blocking Vias

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Solution Overview

Problem

Existing semiconductor packages face challenges in reducing electromagnetic interference (EMI) due to the large mounting area requirements and significant distance between components, which limits their integration and efficiency in mobile devices.

Innovation Solution

A semiconductor package with a connection structure featuring insulating layers, redistribution layers, and redistribution vias that surround passive components to block EMI, allowing for effective electromagnetic interference mitigation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If surface mounting technology (SMT) is used to mount components on a PCB, then components can be individually mounted and replaced, but the mounting area increases and electromagnetic interference (EMI) between components increases

Engineering Contradiction:
Improvecomponent replaceabilityVSAvoidmounting area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent embeds passive components within cavities formed in the substrate, nesting them inside the connection structure rather than mounting them on the surface. This allows multiple components to be integrated in a three-dimensional arrangement, significantly reducing the planar mounting area while maintaining component functionality and replaceability through the embedded configuration.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The invention transitions from two-dimensional surface mounting to three-dimensional embedding by creating cavities within the substrate and placing components inside. This dimensional change allows components to be positioned in vertical space rather than only horizontal space, reducing the overall footprint and mounting area required.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If surface mounting technology (SMT) is used to mount components on a PCB, then components can be individually mounted and replaced, but electromagnetic interference (EMI) between components increases

Engineering Contradiction:
Improvecomponent replaceabilityVSAvoidelectromagnetic interference
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

By nesting passive components within cavities in the substrate, the patent creates a shielded environment that reduces electromagnetic interference. The surrounding substrate material and encapsulant act as barriers to EMI propagation, while the compact embedded arrangement minimizes the distance between components, further reducing interference.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent introduces an encapsulant material that fills the cavities and surrounds the embedded passive components. This encapsulant acts as an intermediary barrier that shields the components from electromagnetic interference while still allowing electrical connections to be made to the components through vias in the substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-generated harmful factors

If components are mounted with large intervals to reduce EMI, then electromagnetic interference decreases, but the mounting area increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoidmounting area
Core Design Contradiction:
Object-generated harmful factorsVSArea of stationary object

Solution Approach 1:

The patent resolves this contradiction by nesting components within the substrate volume rather than spacing them apart on the surface. The embedded configuration allows components to be in close proximity without requiring large surface intervals, as the substrate itself provides the spacing and shielding function that would otherwise require large distances between surface-mounted components.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11329004B2Semiconductor package
Publication Date: 2022.05.10 SAMSUNG ELECTRONICS CO LTD
  • US11329004B2 patent drawing
  • US11329004B2 patent drawing
  • US11329004B2 patent drawing

AI summary

A semiconductor package includes a connection structure having including a plurality of insulating layers and redistribution layers on the plurality of insulating layers. A semiconductor chip has connection pads connected to the redistribution layers, and an encapsulant encapsulates the semiconductor chip. A passive component is embedded in the connection structure and has connection terminals connected to the redistribution layer. The redistribution layers include a plurality of redistribution patterns, each disposed on the plurality of insulating layers and a plurality of redistribution vias each penetrating through the plurality of insulating layers and connected to the plurality of redistribution patterns. The plurality of redistribution vias include a plurality of blocking vias arranged to surround the passive component, and the plurality of redistribution patterns include a blocking pattern connected to adjacent blocking vias.