Embedded Chip Package EMI Shielding via Sidewall Encapsulation
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Solution Overview
Problem
Semiconductor packages face challenges in effectively shielding against electromagnetic interference (EMI) due to the generation of electromagnetic waves and high-frequency noises, which can affect both internal and external systems, particularly in wearable and mobile devices that are closer to human bodies.
Innovation Solution
A semiconductor package design that includes a chip embedded in a dielectric layer with interconnection parts and a shielding plate covering the opposite surface, along with a shielding encapsulation part that extends to cover the sidewalls, providing EMI shielding through a conductive layer and encapsulation structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a shielding structure is added to protect against EMI, then shielding effectiveness is improved, but device complexity increases
Solution Approach 1:
The patent merges the shielding encapsulation part with the circuit interconnection parts by forming both structures simultaneously from the same conductive layer. The shielding encapsulation part and circuit interconnection parts are created in a single patterning process, eliminating the need for separate shielding structures and reducing overall package complexity while maintaining EMI shielding effectiveness.
Solution Approach 2:
The conductive layer serves multiple functions: it forms both the circuit interconnection parts that electrically connect the chip to external circuits and the shielding encapsulation part that provides EMI shielding. This multi-functional approach allows a single structure to perform both electrical connection and electromagnetic interference protection, simplifying the overall package design.
2Object-affected harmful factors
If EMI shielding is enhanced with additional shielding structures, then shielding effectiveness is improved, but manufacturing complexity increases
Solution Approach 1:
The fabrication process merges the formation of shielding encapsulation parts and circuit interconnection parts into a single simultaneous patterning step. The conductive layer is patterned to create both structures at the same time, reducing the number of fabrication steps and simplifying the manufacturing process while ensuring consistent electrical and shielding performance.
3Object-affected harmful factors
If the package structure is expanded to include comprehensive shielding, then shielding effectiveness is improved, but package thickness increases
Solution Approach 1:
The patent transitions from traditional three-dimensional shielding structures (such as separate shielding cans or enclosures) to a two-dimensional planar shielding approach. The shielding encapsulation part is formed as a conductive pattern on the same plane as the circuit interconnection parts, providing EMI shielding without adding vertical thickness to the package.
Data Source
AI summary
A semiconductor package includes a dielectric layer in which a chip is embedded, interconnection parts disposed on a first surface of the dielectric layer, through connectors each of which penetrates a portion of the dielectric layer over the chip to electrically couple the chip to a corresponding one of the interconnection parts, a shielding plate covering a second surface of the dielectric layer that is opposite to the first surface, and a shielding encapsulation part connected to one of the interconnection parts and covering sidewalls of the dielectric layer. The shielding encapsulation part includes a portion contacting the shielding plate.