EMI Shielding Structure in InFO Package for High Density Interconnects
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Solution Overview
Problem
The increasing miniaturization of semiconductor dies and the need for higher I/O pad density in packaging pose challenges, including limited pad numbers due to pitch constraints, solder bridges, and inefficient use of space, especially in fan-in packages, and the inability to effectively manage electromagnetic interference (EMI) in fan-out packages.
Innovation Solution
The development of a package structure that includes a dielectric buffer layer, conductive features, and a shielding structure with dielectric layers and conductive films to redistribute I/O pads and reduce EMI, using a combination of organic and inorganic materials and processes like PVD and electro-less plating to form redistribution lines, side-shielding structures, and antennas, which are encapsulated and planarized to expose the device die and connect it effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fan-in packaging is used to reduce packaging complexity, then device complexity is reduced, but the number of I/O pads is limited due to pitch constraints and solder bridge risks
Solution Approach 1:
The patent transitions from a two-dimensional pad layout (fan-in) to a three-dimensional redistribution structure (fan-out), allowing I/O pads to be redistributed over a larger area through multiple dielectric layers and conductive vias, thereby increasing the number of usable I/O pads without increasing pitch density
2Quantity of substance
If fan-out packaging is used to increase I/O pad density, then the number of I/O pads is increased, but electromagnetic interference management becomes more difficult
Solution Approach 1:
The patent introduces EMI shielding structures as intermediary elements between the I/O pads and the external environment. These shielding structures, positioned within the dielectric layers, act as mediators that block and contain electromagnetic interference while allowing the high-density I/O pad redistribution to function effectively
3Quantity of substance
If I/O pad pitch is decreased to increase pad density, then I/O pad density is improved, but solder bridges may occur
Solution Approach 1:
The patent resolves the solder bridge risk by moving from planar pad arrangement to a multi-layer vertical redistribution architecture. The I/O pads are distributed across multiple dielectric layers and connected through conductive vias, effectively increasing spacing in the horizontal plane while maintaining high connectivity density through the vertical dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased I/O pad density and improved EMI shielding, reducing the risk of solder bridges and enhancing packaging efficiency by redistributing pads and isolating electromagnetic interference, thereby improving yield and reducing costs.
Implementation Method 1
processes like PVD and electro-less plating to form redistribution lines
Implementation Method 2
processes like PVD and electro-less plating to form redistribution lines
Data Source
AI summary
A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.