Semiconductor Package with EMI Shielding Layer
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Solution Overview
Problem
Current three-dimensional integration technologies for wafer-level packaging face challenges in achieving size reduction, high-performance interconnects, and heterogeneous integration for high-density integration packages, particularly in efficiently integrating multiple chips and reducing electromagnetic interference.
Innovation Solution
The method involves forming a semiconductor package by stacking sub-packages with redistribution layers, through vias, and electromagnetic interference shielding layers, using materials like polybenzoxazole and copper, and employing a debonding layer for room temperature separation, which allows for direct chip stacking without connectors, reducing thickness and improving thermal and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional three-dimensional integration technologies are used for wafer-level packaging, then chip stacking is achieved, but package thickness is large and electromagnetic interference occurs
Solution Approach 1:
The patent implements direct chip stacking where multiple chips are vertically integrated without intermediate connectors or underfills. The chips are nested directly onto each other through wafer-level bonding, eliminating the need for separate connector components and reducing overall package thickness while minimizing electromagnetic interference pathways.
Solution Approach 2:
The patent removes traditional connector components and underfill materials from the packaging structure. By extracting these intermediate elements, the design achieves direct chip-to-chip contact, reducing package thickness and eliminating the electromagnetic interference that would be generated by connector assemblies.
2Strength
If connectors and underfills are used in chip stacking, then mechanical connection is achieved, but package thickness increases and thermal performance deteriorates
Solution Approach 1:
The patent merges the functions of mechanical connection, thermal management, and electrical interconnection into a single wafer-level bonding interface. By combining these functions directly at the chip interface without separate connector and underfill components, the design achieves strong mechanical bonding while minimizing package thickness and improving thermal conductivity through direct chip contact.
3Adaptability or versatility
If traditional packaging methods with connectors are used, then chip integration is achieved, but manufacturing complexity increases and production cost rises
Solution Approach 1:
The patent segments the packaging process into wafer-level preparation and direct stacking operations. By preparing chips at the wafer level with integrated bonding interfaces before stacking, the manufacturing process is simplified into fewer discrete steps compared to traditional methods that require separate connector attachment and underfill application steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables significant reduction in package thickness, enhanced thermal and electrical performance, simplified manufacturing, and cost-effective production by eliminating the need for connectors and underfills, while effectively mitigating electromagnetic interference.
Implementation Method 1
the third die and the sub-package are molded by a second molding layer. A second redistribution layer structure is formed over the sub-package, the second die, the third die and the second molding layer... electromagnetic interference shielding layers
Data Source
AI summary
Semiconductor packages and methods of forming the same are provided. a semiconductor package includes a sub-package, a second die and a second molding layer. The sub-package includes a first die, a first molding layer aside the first die and a first redistribution layer structure disposed over the first die and the first molding layer and electrically connected to the first die. The second die is disposed over the sub-package, wherein the first die and the second die are disposed on opposite surfaces of the first redistribution layer structure. The second molding layer encapsulates the sub-package and the second die.