EMIB Interconnect Bridge Layout for Higher-Density Multi-Die Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current microelectronic device technologies are limited in the number of chips or dies that can be interconnected due to the size constraints of silicon chips, restricting the complexity and capability of multi-die packages.
Innovation Solution
The implementation of embedded multi-die interconnect bridges (EMIBs) that are embedded into the substrate during manufacturing, allowing for rapid communication between dies and incorporating components like metal resistors and capacitors to reduce size and increase efficiency, enabling more complex circuitry and heterogeneous die configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional silicon chip interconnection methods are used, then the manufacturing process is simple, but the number of chips or dies that can be interconnected is limited due to size constraints
Solution Approach 1:
The patent divides the interconnection system into separate components: small active dies and a larger interposer substrate. The interposer acts as an intermediary that segments the interconnection function from the active circuitry, allowing multiple dies to be connected without increasing individual die size. This segmentation enables scaling to more dies by adding interposer real estate rather than increasing die dimensions.
Solution Approach 2:
The interposer substrate serves as an intermediary component between multiple dies. It provides additional interconnection resources and routing capacity that would otherwise require larger individual dies. The interposer mediates the connections between dies, enabling high-density interconnection without constraining the size of individual active dies.
2Productivity
If more interconnections are added between dies, then communication capability increases, but the size of silicon chips must increase
Solution Approach 1:
The patent moves the interconnection capacity from the two-dimensional plane of individual dies to the three-dimensional stack architecture. By placing interconnect bridges and routing resources on separate interposer layers between dies, the system adds interconnection capacity in the vertical dimension rather than expanding horizontal die area. This enables high communication efficiency without increasing chip footprint.
Solution Approach 2:
The interposer substrate acts as an intermediary that provides additional interconnection resources and routing capacity. It absorbs the complexity of high-density interconnections, allowing individual dies to remain compact while achieving enhanced communication efficiency through the interposer-mediated connection network.
3Adaptability or versatility
If die size is reduced to fit more dies, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The interposer substrate serves as a tolerant intermediary platform that can accommodate larger dimensional variations. By placing alignment markers and reference features on the interposer rather than on small dies, the system relaxes alignment precision requirements. The interposer acts as a buffer that absorbs manufacturing tolerances, enabling high integration density without proportionally increasing precision demands.
4Ease of manufacture
If traditional interconnection methods are used, then manufacturing process is simple, but production costs increase due to larger chip sizes
Solution Approach 1:
The patent segments the manufacturing process into modular stages: die fabrication, interposer fabrication, and assembly bonding. This segmentation allows each component to be optimized independently and manufactured in high volumes, improving economies of scale. The interposer can be manufactured separately using cost-effective substrates, reducing the need for expensive large-die fabrication while maintaining manufacturing simplicity through standardized processes.
Data Source
AI summary
An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.