EMIB Bridge Packages With Lithographic Bumps for Sub-40 µm Pitch
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Solution Overview
Problem
Semiconductor device miniaturization faces challenges in bump-pitch scaling, making it difficult to locate close-pitch electrical bumps on semiconductor package surfaces effectively.
Innovation Solution
The development of embedded multi-die interconnect bridge (EMIB) packages that utilize lithographically formed bumps and semi-additive plating processes to achieve bump-pitch scaling below 40 micrometers, with controlled bump-thickness variation and package-substrate thickness, allowing for modular die-fabric interconnects and high-yield packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional bump formation methods are used, then manufacturing simplicity is maintained, but bump-pitch scaling below 40 micrometers cannot be achieved
Solution Approach 1:
The bump formation process is segmented into multiple distinct stages: lithographic patterning to define bump locations, semi-additive plating to build conductive structures, and controlled deposition to form final bumps. This segmentation enables precise control over bump pitch while maintaining manufacturability through standardized process modules.
Solution Approach 2:
Lithographic patterns are formed in advance to precisely define bump locations and pitches before any metal deposition occurs. This preliminary patterning action establishes the geometric framework that guides subsequent plating and bump formation processes, enabling sub-40 micrometer pitch accuracy.
2Manufacturing precision
If bump pitch is reduced to enable miniaturization, then device density increases, but control over bump-thickness variation and package-substrate thickness becomes difficult
Solution Approach 1:
The process incorporates feedback control through planarization steps that measure and compensate for thickness variations in real-time. By monitoring film thickness during deposition and adjusting subsequent processing parameters, the system maintains consistent bump and substrate thickness even as pitch dimensions are reduced.
Solution Approach 2:
Processing parameters such as deposition rate, plating current density, and etch selectivity are precisely adjusted and optimized for each layer and material combination. These parameter changes enable control over film thickness at sub-40 micrometer pitches, preventing variation accumulation as device dimensions shrink.
3Manufacturing precision
If lithographic processes are used to form bumps, then bump-pitch scaling precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The lithographic process is designed to perform multiple functions: defining bump locations, establishing alignment references for subsequent layers, and creating patterns for interconnect routing. This multi-functionality reduces the need for separate processing steps, offsetting the complexity of using lithography with sub-40 micrometer resolution.
4Volume of moving object
If close-pitch electrical bumps are located on semiconductor package surfaces, then device miniaturization is achieved, but assembly and testing yield decreases
Solution Approach 1:
The process incorporates built-in compensation features such as alignment margins, tolerance budges in the design, and robust attachment mechanisms that anticipate and accommodate variations in bump placement and substrate dimensions. This beforehand cushioning protects assembly yield even as pitch dimensions are reduced for miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the successful assembly and testing of multi-die semiconductor packages with precise bump-pitch scaling, improving the yield and reliability of semiconductor packaging by controlling film thickness and material shrinkage variations, and facilitating communication between multiple dies through a bridge die.
Implementation Method 1
lithographically formed bumps
Implementation Method 2
semi-additive plating processes
Data Source
AI summary
An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.