EMIB Multichip Package Configurable Adapter Circuitry
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Solution Overview
Problem
Conventional multichip packages face challenges in supporting high-speed networking protocols due to costly and mechanically prone interposer substrates, limited flexibility, and restricted data transfer capabilities, particularly in applications like data centers and IoT, which require higher bandwidth and flexibility while minimizing power consumption.
Innovation Solution
A multichip package design featuring a main integrated circuit die coupled to an auxiliary transceiver die via Embedded Multi-die Interconnect Bridge (EMIB) with configurable adapter circuitry, including FIFO circuits that support various communication protocols and data widths, operating in different modes to enhance data transfer efficiency and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interposer substrates are used to connect multiple dies, then mechanical support and routing are provided, but manufacturing cost increases and mechanical issues such as warpage occur
Solution Approach 1:
The patent removes the interposer substrate from the multichip package structure, directly connecting dies to the package substrate through solder bumps. This extraction eliminates the source of warpage and reduces manufacturing complexity while maintaining mechanical support through direct die-to-substrate attachment.
Solution Approach 2:
The package substrate is designed to directly provide both mechanical support and signal routing functions that were previously separated between the interposer and package substrate. The substrate incorporates routing traces that can accommodate multiple protocol types (PCIe, USB, SATA, SAS), eliminating the need for protocol-specific interposers.
2Adaptability or versatility
If interposer substrates with logic routing fabric are used, then interconnection between dies is enabled, but interconnect length increases and loading on driver buffers increases
Solution Approach 1:
The complex logic routing fabric of the interposer is removed. Instead, simple point-to-point or point-to-multipoint routing traces are implemented directly on the package substrate, dramatically reducing interconnect length and signal path complexity while maintaining full interconnection capability between all dies.
3Speed
If conventional multichip packages are designed for high-speed networking, then data transfer capability is achieved, but flexibility is limited and single protocol support is enforced
Solution Approach 1:
The package substrate is designed with universal routing traces and buffer structures that can accommodate multiple high-speed protocols (PCIe, USB 3.0/3.1, SATA, SAS) simultaneously. The same physical infrastructure supports different protocol standards, allowing the system to be configured for different applications without redesigning the package architecture.
Solution Approach 2:
The system incorporates programmable buffer circuits and configurable adapter logic that can be dynamically programmed to support different protocol requirements. This dynamic reconfigurability allows the same hardware infrastructure to adapt to different data widths, clock rates, and protocol specifications as needed.
4Productivity
If multiple dies are placed laterally or stacked to increase integration, then performance and density improve, but design complexity and manufacturing difficulty increase
Solution Approach 1:
The system uses standardized die packages with uniform mounting interfaces that can be independently fabricated and tested before final assembly. This segmentation allows each die to be optimized separately while maintaining a simple, modular package structure that reduces overall design and manufacturing complexity.
Data Source
AI summary
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de) compressed data streams.