EMIB Patch FLI-First Carrier Layout for Micro-Bump Uniformity
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Solution Overview
Problem
Current EMIB substrate manufacturing processes face challenges in achieving uniformity and precision in micro-bump thickness variation (BTV) due to the complexity of panel-level planarization and lithography steps, which are costly and hard to control, especially with the trend towards smaller bump pitches.
Innovation Solution
The first layer interconnect (FLI) is formed on a smooth glass carrier, allowing precise control of bump thickness and reducing variations by flipping the bridge die for direct connection, eliminating the need for subsequent lithography steps and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If panel-level planarization and lithography steps are used in EMIB substrate manufacturing, then interconnect precision can be achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-forming the first layer interconnect (FLI) on a carrier substrate before attaching the bridge die. This preliminary formation of interconnect structures on a separate carrier allows for precise thickness control to be established early in the process, eliminating the need for complex post-attachment planarization and lithography steps to achieve the required precision.
2Quantity of substance
If smaller bump pitches are used to meet I/O density requirements, then interconnect density increases, but bump thickness variation control becomes more difficult
Solution Approach 1:
The patent segments the manufacturing process by separating the FLI formation on a carrier substrate from the bridge die attachment. This segmentation allows the interconnect structures to be formed with precise thickness control in a dedicated process step on the carrier, independent of the subsequent die attachment process. The carrier substrate acts as a separate platform that enables precise micro-bump formation even at smaller pitches, which is then integrated with the bridge die in a later step.
Data Source
AI summary
A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.