EMIB Patch FLI-on-Carrier Layout for Low Bump Thickness Variation
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Solution Overview
Problem
The challenge in creating first layer interconnects (FLI) for EMIB substrates is the stringent bump thickness variation (BTV) requirements due to small micro-bump pitching, which complicates the manufacturing process and requires expensive panel level planarization, especially when forming bumps on top of multiple build-up layers.
Innovation Solution
The FLI is created first on a smooth glass carrier, allowing precise control of bump thickness and reducing variations by flipping the bridge die face down for attachment, eliminating the need for subsequent lithography steps and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bumps are formed on top of multiple build-up layers to meet I/O density requirements, then bump pitch can be reduced to achieve higher density, but bump thickness variation (BTV) becomes difficult to control and panel level planarization is required
Solution Approach 1:
The patent performs planarization of the build-up layers before forming the bumps, ensuring a flat surface for bump deposition. This preliminary action prevents thickness variation issues that would otherwise require expensive panel level planarization later in the process, while enabling high density bump placement.
Solution Approach 2:
The patent uses a carrier substrate as a template or copy surface where the build-up layers are formed with precise thickness control. The carrier serves as a reference plane that is replicated across the entire substrate, ensuring uniform bump thickness without requiring complex in-situ planarization equipment.
2Manufacturing precision
If panel level planarization is performed to control BTV, then manufacturing precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the planarization function from the main manufacturing process by performing it on a separate carrier substrate before bump formation. This separation allows the use of simpler, more cost-effective planarization techniques on the carrier rather than requiring complex panel level planarization equipment for the final substrate.
Solution Approach 2:
The carrier substrate acts as an intermediary that provides a pre-planarized surface for bump formation. By using this intermediate carrier, the patent avoids the need for direct panel level planarization of the final substrate, simplifying the overall manufacturing process while maintaining BTV control.
3Quantity of substance
If micro-bump pitch is reduced to meet I/O density requirements, then I/O density increases, but manufacturing complexity and BTV control difficulty increase
Solution Approach 1:
The patent performs preliminary planarization of the build-up layers on the carrier substrate before depositing the micro-bumps. This advance preparation creates a uniform surface that simplifies the subsequent bump formation process, allowing high density placement without increasing manufacturing complexity.
Solution Approach 2:
The carrier substrate serves as a template that replicates the desired bump pattern and spacing across the entire substrate. This copying approach enables consistent micro-bump placement at high density while maintaining ease of manufacture through standardized processes.
Data Source
AI summary
A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.