Emission Driver Buffer Circuit for Sequential and Simultaneous Modes

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Solution Overview

Problem

Typical emission drivers struggle to generate proper emission control signals for various display modes, such as sequential and simultaneous emission modes, and face difficulties in controlling duty rates due to driver circuit configuration.

Innovation Solution

An emission driver with multiple stages, each comprising a first driving block, a second driving block, and a buffer block, which receives input and clock signals to output intermediate signals and ultimately generate emission control signals that can operate in either sequential or simultaneous emission modes by adjusting voltage levels and timing, allowing for synchronized edges and controlled duty ratios.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a typical emission driver circuit configuration is used, then the circuit structure is simple, but it cannot generate proper emission control signals for various display modes (sequential and simultaneous emission modes) and cannot control duty rate

Engineering Contradiction:
Improvedisplay mode compatibilityVSAvoiddriver circuit configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The emission driver is divided into multiple stages (first stage, second stage, etc.), where each stage contains driving blocks and buffer blocks that process signals independently. This segmentation allows each stage to contribute to generating emission control signals for different display modes, enabling the system to support both sequential and simultaneous emission modes while maintaining manageable circuit complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The driving blocks and buffer blocks are designed with multi-functional capabilities to handle different display modes. The same circuit blocks can operate in different configurations to generate emission control signals for sequential emission mode, simultaneous emission mode, and other display modes, making the driver circuit universal and adaptable without requiring separate dedicated circuits for each mode

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the emission driver uses multiple stages with driving blocks and buffer blocks, then it can generate proper emission control signals for different display modes, but the circuit complexity increases

Engineering Contradiction:
Improvedisplay mode compatibilityVSAvoiddriver circuit configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The emission driver is divided into multiple stages (first stage, second stage, etc.), where each stage contains driving blocks and buffer blocks that process signals independently. This segmentation allows each stage to contribute to generating emission control signals for different display modes, enabling the system to support both sequential and simultaneous emission modes while maintaining manageable circuit complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple driving blocks (first driving block, second driving block, etc.) and buffer blocks are combined within each stage to work together in generating emission control signals. The driving blocks process different input signals (first input signal, second input signal, clock signals) and the buffer blocks combine their outputs, merging multiple signal processing functions into a unified stage structure that achieves complex display mode support through coordinated operation

Inventive Principle:
Principle #5Merging (Combining)

3Ease of operation

If the buffer block determines duration based on interval between intermediate signals, then duty rate control is achieved, but the timing precision requirements increase

Engineering Contradiction:
Improveduty rate controlVSAvoidtiming precision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The buffer block uses the timing relationship between intermediate signals from driving blocks as feedback to determine the duration of emission control signals. By monitoring when intermediate signals transition between voltage levels, the buffer block automatically adjusts the duty rate based on the measured time intervals, providing ease of operation through automatic duty rate control while the circuit itself handles the precision timing measurements

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The driving blocks and buffer blocks automatically generate and process timing signals without requiring external intervention. The buffer block self-determines the duration of emission control signals by measuring the interval between intermediate signal transitions, and the circuit automatically adjusts duty rates based on these measurements, making the system self-sufficient in handling timing precision requirements

Inventive Principle:
Principle #25Self-service

Data Source

PatentEP3410424B1Emission driver and display device including the same
Publication Date: 2020.01.29 SAMSUNG DISPLAY CO LTD
  • EP3410424B1 patent drawingFigure 1
  • EP3410424B1 patent drawingFigure 2
  • EP3410424B1 patent drawingFigure 3A

AI summary

An emission driver and a display device having the same are disclosed. In one aspect, the emission driver includes a plurality of stages each configured to output an emission control signal, wherein each of the stages includes first and second driving blocks and a buffer block. The buffer block is configured to selectively output an emission control signal so as to operate in a sequential emission mode or in a simultaneous emission mode, the stages being configured to sequentially output a plurality of the emission control signals in the sequential emission mode and substantially simultaneously output the emission control signals in the simultaneous emission mode. The buffer block is further configured to determine a duration in which the emission control signal has a first voltage level based on an interval between time points when first and second intermediate signals have low voltage levels.