Emitter Array Layout to Prevent Structure Overlap
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Solution Overview
Problem
Existing emitter arrays face challenges in achieving close spacing between emitters due to overlapping structures, which limits manufacturing tolerances and increases chip size, thereby affecting the density of emitters per chip.
Innovation Solution
The proposed solution involves optimizing the layout of emitter arrays by configuring emitters such that different types of structures between adjacent emitters do not overlap, while maintaining close spacing. This is achieved through techniques such as rotating emitters to align like structures, adjusting the size and shape of structures, and connecting shared structures between emitters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If emitters are arranged in a conventional grid layout, then the manufacturing process is simple, but the distance between emitters is large and emitter density is low
Solution Approach 1:
The patent applies asymmetry by rotating adjacent emitters by different angles (e.g., 0°, 15°, 30°, 45°) relative to the substrate. This asymmetric orientation causes the structures of adjacent emitters to interlock or nest together, reducing the distance between emitters and increasing emitter density on the chip.
Solution Approach 2:
The patent transitions from a conventional two-dimensional grid layout to a three-dimensional spatial arrangement by varying the rotational angles of emitters in different layers or positions. This dimensional change allows emitters to be packed more densely by utilizing angular displacement as an additional degree of freedom.
2Productivity
If emitters are placed close together, then emitter density increases, but structures of adjacent emitters overlap causing manufacturing difficulties
Solution Approach 1:
By rotating adjacent emitters by different asymmetric angles, the patent ensures that the structures of neighboring emitters do not align in a way that causes overlap. The asymmetric orientation creates staggered positions for critical structures like mesas, contacts, and optical apertures, thereby maintaining manufacturing precision while achieving close spacing.
Solution Approach 2:
The patent performs preliminary rotational positioning of emitters during the design and fabrication planning stage. By pre-determining the optimal rotation angles for each emitter based on its position in the array, the design ensures that structures will not overlap during subsequent manufacturing processes, thus maintaining precision without requiring complex real-time adjustments.
3Area of stationary object
If conventional emitter layouts are used, then manufacturing tolerances are relaxed, but chip size increases reducing the number of emitters per chip
Solution Approach 1:
The asymmetric rotation of emitters creates a compact arrangement where the projected footprint of each emitter is optimized. By angling the emitters, the effective area occupied by each emitter and its associated structures is reduced, allowing more emitters to fit on a single chip while maintaining adequate spacing tolerances through the staggered configuration.
Solution Approach 2:
The patent utilizes angular displacement as an additional dimension to pack emitters more efficiently. Instead of only varying positions in the x-y plane, the emitters are distributed in three-dimensional orientation space, effectively reducing the two-dimensional chip area required for a given number of emitters.
Data Source
AI summary
A closely spaced emitter array may include a first emitter comprising a first plurality of structures and a second emitter, adjacent to the first emitter, comprising a second plurality of structures. The first emitter and the second emitter may be configured in the closely spaced emitter array such that different types of structures between the first plurality of structures and the second plurality of structures do not overlap while maintaining close spacing between the first emitter and the second emitter.