Emitter Follower Buffer with Load Replication for High Linearity
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Solution Overview
Problem
Existing source/emitter follower buffer circuits face challenges in achieving high linearity and high input impedance while driving low impedance loads, particularly in applications like high-speed switched capacitor-based analog-to-digital converters, with existing solutions either introducing distortion or requiring high input impedance.
Innovation Solution
A buffer circuit topology is introduced, featuring an input stage and an output stage with a current source circuit, where a load representation is placed between the stages to improve linearity and input impedance, utilizing cascode transistors and a feedforward mechanism to replicate the output load, allowing for improved linearity even with complex loads like filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dummy capacitive load is added to improve linearity, then linearity is improved, but input impedance decreases
Solution Approach 1:
An input stage buffer is introduced as an intermediary between the high-impedance signal source and the dummy capacitive load. This buffer isolates the signal source from the low-impedance load effect while still allowing the dummy load to function for linearity improvement. The buffer's high input impedance preserves the original signal source characteristics, while its output drives the dummy load effectively.
Solution Approach 2:
The circuit is divided into distinct functional stages: an input stage with high impedance for signal reception, a buffer stage for impedance transformation and isolation, and an output stage with the dummy capacitive load for linearity improvement. This segmentation allows each stage to optimize its function without compromising the others.
2Use of energy by moving object
If bias current is reduced to save power, then power consumption is reduced, but ability to drive low impedance load deteriorates
Solution Approach 1:
The dummy capacitive load is connected in parallel with the output load before the signal needs to be driven. This pre-positioned capacitance anticipates and compensates for the current demands of low-impedance loads, allowing the buffer to maintain adequate drive capability even at reduced bias currents. The dummy load effectively prepares the circuit for subsequent load variations.
Solution Approach 2:
The circuit utilizes the reactive parameter (capacitance) of the dummy load to compensate for reduced real power availability. By changing the approach from purely resistive power delivery to including reactive energy storage, the circuit maintains load driving capability with lower bias current. The dummy capacitor stores and releases energy to supplement the reduced bias current during high-demand periods.
3Manufacturing precision
If circuit complexity is increased to improve linearity, then linearity is improved, but device complexity increases
Solution Approach 1:
A dummy capacitive load that replicates or copies the characteristics of the actual output load is introduced. This copy allows the circuit to anticipate and compensate for load effects without requiring complex real-time control mechanisms. The simplified copying approach achieves linearity improvement through a straightforward parallel capacitance addition rather than complex feedback or modulation circuits.
Data Source
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Figure 5A~6
AI summary
In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.