e.MMC Command Queuing for Higher Throughput Memory Transfers
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Solution Overview
Problem
Existing memory systems face limitations in managing operations due to resource constraints, leading to inefficiencies in command execution and data transfer, particularly in systems utilizing the e.MMC protocol.
Innovation Solution
Introduce new command classes (CMD 43-47) within the e.MMC protocol to enable command queuing and concurrent command execution, allowing for improved management of command queues and data transfers through a modified state machine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple commands are sent sequentially to a memory device, then data transactions can be performed, but command queuing delays may cause performance degradation and timing issues
Solution Approach 1:
The system pre-establishes a queue of commands before executing them. Commands are prepared and ordered in advance, allowing the memory device to process them efficiently without delays. The host system maintains a command queue that is populated beforehand, ensuring continuous operation and reducing waiting time during data transactions.
Solution Approach 2:
The system implements feedback mechanisms where the host receives responses from the memory device and uses this information to manage command queuing. The feedback loop allows the host to track command status, adjust queuing timing, and optimize data transaction flow, thereby reducing queuing delays while maintaining high throughput.
2Productivity
If commands are queued to improve data transaction efficiency, then throughput increases, but command timing and synchronization become more complex
Solution Approach 1:
The command queuing system is segmented into distinct phases: command preparation, command transmission, response reception, and next command initiation. This segmentation allows each phase to be managed independently, simplifying the overall timing synchronization while maintaining high throughput. The host system divides the complex queuing process into manageable segments with clear boundaries.
Solution Approach 2:
The command queuing mechanism is made dynamic, allowing the host to adjust queuing parameters based on real-time conditions. The system can dynamically modify command timing, queue depth, and synchronization points according to memory device response characteristics, thereby managing complexity through adaptability rather than rigid fixed timing.
3Reliability
If the host waits for command responses before sending next commands, then data transaction accuracy is maintained, but overall system speed decreases
Solution Approach 1:
The host system prepares and queues multiple commands in advance while waiting for responses to previous commands. This preliminary action allows the next command to be ready and sent immediately upon receiving the previous response, maintaining accuracy through proper sequencing while improving overall speed by eliminating idle waiting time.
Solution Approach 2:
The system maintains continuous useful action by overlapping command preparation and response waiting periods. While the memory device processes a command, the host simultaneously prepares the next command in the queue. This continuity ensures that commands are sent back-to-back without unnecessary delays, maintaining both accuracy through proper timing and speed through continuous operation.
Data Source
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Figure 4A~4B
AI summary
A method for command queuing is disclosed. The method comprises: identifying and sending, by a host, a first command to be queued at a memory device; receiving, by the host, a first response to the first command from memory device; sending, by the host, a second command to the memory device in response to receiving the first response; sending, by the host, a third command to execute a data transaction in response to receiving the first response and the second response; receiving, by the host, a third response to the third command from memory device; and transferring data to or reading data from memory device in response to receiving the third response from memory device.