eMMC Delay Offset Adjustment for Timing Skew

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Solution Overview

Problem

Embedded Multimedia Cards (eMMCs) face challenges in securing an improved data valid window due to timing skew issues when communicating with hosts, particularly at high clock speeds like in the DDR 400 mode, which affects data transmission speed and reliability.

Innovation Solution

The eMMC system employs a method to adjust data signal delays using delay offset values stored in the EXT_CSD register, with a host transmitting a SWITCH command and Get Tuning Block command to determine valid data signals and set optimal delay offsets, and includes delay circuits to adjust clock and data signals based on calculated codes for improved timing alignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data signals are transmitted at high clock speeds (DDR 400 mode), then data transmission speed is improved, but timing skew between clock and data signals increases causing data validity issues

Engineering Contradiction:
Improvedata transmission speedVSAvoiddata signal validity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing delay adjustment before data transmission. The host controller sends a SWITCH command with delay offset values to the eMMC, which then adjusts the delay of data signals using delay circuits before actual data transfer occurs. This pre-adjustment ensures proper timing alignment is established in advance, preventing timing skew issues during high-speed operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements parameter changes by dynamically modifying the delay parameter of data signals. The eMMC receives delay offset values and changes the delay parameter of its data signals accordingly. This allows the system to optimize timing parameters for different operating conditions and clock speeds, maintaining data validity while enabling high-speed transmission.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If delay adjustment is performed to correct timing skew, then data signal validity is improved, but system complexity increases due to additional control commands and delay circuits

Engineering Contradiction:
Improvedata signal validityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by making the SWITCH command multi-functional. The existing SWITCH command, traditionally used for mode switching, is extended to also carry delay offset values for timing adjustment. This allows the system to perform both mode switching and delay adjustment using a single command mechanism, reducing the need for separate control structures and minimizing system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The eMMC performs self-service by automatically adjusting its own data signal delays based on received offset values. The delay circuits within the eMMC are controlled locally using the provided delay parameters, eliminating the need for external delay adjustment circuitry in the host. This self-adjusting capability simplifies the overall system architecture while maintaining reliable timing alignment.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9772651B2Embedded multimedia card (eMMC), host controlling eMMC, and method operating eMMC system including the use of a switch command defining an adjustment delay for a data signal
Publication Date: 2017.09.26 SAMSUNG ELECTRONICS CO LTD
  • US9772651B2 patent drawing
  • US9772651B2 patent drawing
  • US9772651B2 patent drawing

AI summary

An embedded multimedia card (eMMC) is provided. The eMMC includes a clock channel receiving a clock output from a host, data channels receiving data signals from the host, and a command channel receiving a SWITCH command including delay offset values from the host so as to adjust a delay of at least one of the data signals, which are received, in response to the delay offset values.