eMMC Multi-Queue Command Registers for Data Transmission Speed
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Solution Overview
Problem
Conventional embedded Multimedia Cards (eMMCs) face challenges in maintaining an optimal data valid window due to limitations in input timing correction for data signals, leading to inefficiencies in data communication with hosts, particularly in dual data rate modes.
Innovation Solution
The introduction of an additional signal line in the standard 10-wire configuration enhances noise immunity and transmission speed by allowing for multi-queue command and data operations, enabling simultaneous processing of multiple commands and data transfers, thereby improving read and write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional eMMC uses standard 10-wire configuration without additional signal lines, then device complexity is low, but data transmission speed and noise immunity are limited
Solution Approach 1:
The patent segments the command processing function into multiple independent command registers (CMD0-CMD7), allowing parallel command queuing and processing. This segmentation enables the eMMC to handle multiple commands simultaneously, improving data transmission speed without requiring additional physical signal lines beyond the standard 10-wire configuration.
Solution Approach 2:
The patent introduces a time-multiplexed command queue dimension by implementing multiple command registers that can be filled and executed in sequence. This adds a temporal processing dimension to the command interface, allowing the system to achieve higher throughput by processing commands in parallel queues rather than sequential single-command mode.
2Productivity
If eMMC processes commands sequentially with single command register, then device complexity is low, but idle time between commands increases reducing productivity
Solution Approach 1:
The patent implements preliminary action by allowing the host to pre-fill multiple command registers (CMD0-CMD7) with upcoming commands before the eMMC finishes executing current commands. This command queuing mechanism eliminates idle waiting time, as the eMMC can continuously process commands from the filled registers without pausing for host intervention, thereby improving productivity.
Solution Approach 2:
The multi-command register structure enables continuous useful action by maintaining an uninterrupted command stream. The eMMC controller can continuously fetch and execute commands from the command registers without idle gaps, ensuring that the data interface remains constantly productive. This continuity is achieved through the overlapping execution of multiple commands in parallel queues.
3Productivity
If eMMC uses standard input timing correction, then device complexity is low, but data valid window is insufficient leading to communication inefficiencies
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the data valid window timing parameters based on the command execution state and data readiness. The eMMC controller modifies the timing parameters of the data valid window to ensure optimal alignment with the host's data sampling points, improving communication efficiency without requiring complex additional hardware correction circuits.
Data Source
AI summary
A method of operating an eMMC system includes receiving a first command defining a first operation from the host, and storing the first command in a first command register among N command registers, and receiving a second command defining a second operation from the host, and storing the second command in a second command register among the N command registers, wherein the second command is received while the first operation is being performed.