Emulated DOCSIS Clock for R-PHY Latency Reduction
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Solution Overview
Problem
In R-PHY networks, the synchronization of clocks between the CCAP core and Remote PHY Devices (RPDs) is challenging due to the discrepancy between the 204.8 MHz hardware clock used by Precision Timing Protocol (PTP) and the 10.24 MHz clock required by the DOCSIS standard, leading to latency and reduced packet forwarding rates caused by costly sampling and contention issues.
Innovation Solution
Implementing an emulated DOCSIS clock in RPDs, which uses a high-frequency FPGA clock to generate a low-frequency DOCSIS clock through sampling and adjustment, reducing the need for direct hardware access and minimizing latency by calculating an average adjustment factor to convert the CPU time to a 10.24 MHz DOCSIS time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If direct hardware clock sampling is used to convert 204.8 MHz PTP clock to 10.24 MHz DOCSIS clock, then clock synchronization is achieved, but latency increases and packet forwarding rate decreases due to costly sampling and contention
Solution Approach 1:
The system pre-calculates and stores an average adjustment factor by sampling the hardware clock multiple times during an initialization period. This preliminary action eliminates the need for continuous real-time sampling during packet forwarding, thereby resolving the contradiction between achieving accurate clock synchronization and maintaining high packet forwarding rates.
2Measurement precision
If frequent hardware clock sampling is performed to maintain synchronization accuracy, then clock synchronization is improved, but system latency increases and processing efficiency decreases
Solution Approach 1:
The adjustment factor is calculated in advance during a calibration phase, eliminating the need for continuous real-time sampling. This preliminary computation stores the timing relationship in a lookup table, allowing the software clock to maintain synchronization accuracy without introducing latency during actual packet processing operations.
3Loss of information
If direct hardware access for clock sampling is implemented, then accurate timing information is obtained, but contention issues arise and processing efficiency is reduced
Solution Approach 1:
The system performs hardware clock sampling and stores the average adjustment factor during an initialization or calibration period when packet forwarding demand is low. This preliminary action captures the timing relationship between hardware and software clocks, allowing subsequent operations to use the pre-computed factor without contending for hardware resources during high-load packet processing.
Solution Approach 2:
Instead of continuously accessing the hardware clock during packet forwarding, the system creates a software-based copy of the clock using the pre-calculated adjustment factor. This virtual clock copy provides timing information without requiring repeated hardware access, thereby eliminating contention issues while maintaining timing accuracy.
Data Source
AI summary
Systems and methods for implementing a software emulation of a clock calibrated by the software based on sampling a hardware clock.