Emulating Fused Multiply-Add Operations Without Specialized Adders
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Solution Overview
Problem
Existing hardware requires a specialized 51-bit adder to perform FMA operations, which increases space and power requirements and can lead to critical path issues, while unfused multiply-add operations provide inaccurate results due to rounding errors.
Innovation Solution
Emulating FMA operations using existing hardware by dividing the intermediate product into upper and lower portions, allowing the third operand to be added to either portion using normal adder hardware, and combining the results to produce an emulated FMA result without the need for a specialized adder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a specialized 51-bit adder is used to perform FMA operations, then measurement precision is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent segments the intermediate product into upper and lower portions, each processed separately with standard adders. This segmentation allows the use of existing hardware resources while achieving FMA precision through coordinated processing of the segmented parts, thereby avoiding the need for a specialized 51-bit adder.
Solution Approach 2:
The patent introduces intermediate values (upper and lower portions) as mediators between the multiplication operation and the final addition. These intermediates are processed through standard adders in a coordinated manner, enabling FMA functionality without requiring a specialized adder hardware component.
2Measurement precision
If a specialized 51-bit adder is used to perform FMA operations, then measurement precision is improved, but power consumption increases
Solution Approach 1:
By segmenting the addition operation into processing upper and lower portions separately using standard adders, the patent reduces the power consumption compared to a specialized 51-bit adder. The standard adders consume less power individually, and their coordinated operation achieves the same FMA precision with lower overall power consumption.
3Device complexity
If unfused multiply-add operation is used, then device complexity is reduced, but measurement precision deteriorates due to rounding errors
Solution Approach 1:
The patent segments the intermediate product into upper and lower portions and processes them through coordinated addition operations. This segmentation approach maintains hardware simplicity by using standard adders while improving precision by avoiding the rounding errors inherent in unfused operations, achieving FMA accuracy without specialized hardware.
Solution Approach 2:
The patent maintains continuity of precision by processing the upper and lower portions through coordinated operations that preserve the full precision of the intermediate product. This continuous processing approach ensures that no precision is lost during the addition process, achieving FMA accuracy while keeping device complexity low.
Data Source
AI summary
At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.