Emulated Memory Rewind via Log Memory Segmentation
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Solution Overview
Problem
Current hardware logic emulation systems face challenges in providing comprehensive visibility into design signals over time for debugging integrated circuit designs, particularly in identifying which signals to observe and when, due to the complexity and size of digital circuits, leading to inefficiencies in simulation and emulation processes.
Innovation Solution
The implementation of a logic emulation system that includes a log memory associated with emulated memory, allowing for the restoration of emulated memory circuits to a predetermined time by marking log memory locations as valid or invalid, enabling efficient data capture and rewind functionality without interrupting the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the trace window size is increased to provide comprehensive visibility into design signals over time, then debugging capability is improved, but memory requirements and system complexity increase
Solution Approach 1:
The patent segments the trace window into multiple fixed-size segments, each associated with a segment identifier. Instead of maintaining a single large memory structure for the entire trace window, the system divides it into manageable segments that can be independently managed and accessed. This segmentation reduces the complexity of managing large trace windows while preserving comprehensive visibility into design signals over time.
Solution Approach 2:
The patent pre-allocates fixed-size segments and establishes segment boundaries before the trace window is fully populated. Segment identifiers are assigned in advance, and the segment association logic is prepared beforehand. This preliminary structuring allows the system to handle large trace windows efficiently without requiring complex dynamic memory management during operation, thus reducing overall system complexity.
2Loss of information
If the trace window size is increased to capture more design signals over time, then debugging capability is improved, but memory requirements increase
Solution Approach 1:
By dividing the trace window into fixed-size segments, the patent enables efficient memory utilization. Each segment can be independently managed and reused when no longer needed. This segmentation allows the system to maintain comprehensive signal visibility over extended time periods without requiring proportionally increasing memory resources, as old segments can be overwritten or discarded.
Solution Approach 2:
The patent implements a mechanism where completed or obsolete trace segments are discarded and their memory resources recovered for reuse. The segment association logic identifies which segments are no longer needed for debugging analysis and makes their memory available for new trace data. This discarding and recovering process prevents memory exhaustion while maintaining the ability to capture comprehensive design signal information.
3Loss of information
If free running simulation with signal dump is used to capture all signals during simulation, then comprehensive visibility is achieved, but simulation speed decreases
Solution Approach 1:
The patent extracts only the essential segment identification information from the trace data rather than dumping all signal values during simulation. By separating the segment metadata (identifiers, boundaries, associations) from the actual signal data, the system achieves comprehensive visibility into design signals over time while maintaining simulation speed, as the extraction overhead is minimal compared to full signal dumping.
Solution Approach 2:
The patent creates a lightweight copy of segment metadata (identifiers and boundaries) rather than copying actual signal data during simulation. This metadata copy is sufficient for later analysis and debugging, enabling comprehensive signal visibility without the performance penalty of copying or storing complete signal waveforms during the simulation process.
Data Source
AI summary
Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.