Emulated Multiport Memory via XOR Control and Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dual-port memory elements in integrated circuits limit memory access bandwidth and speed due to their inability to support multiple read or write operations simultaneously, which is inadequate for complex or high-speed operations requiring multiple memory requests.
Innovation Solution
Implementing multiple dual-port memory elements with switching circuitry controlled by XOR-based logic to emulate a multi-port memory element with multiple read and write ports, allowing concurrent data access and increased bandwidth and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual-port memory elements are used, then the memory structure is simple and resource consumption is reduced, but memory access bandwidth and speed are limited due to inability to support multiple concurrent operations
Solution Approach 1:
The patent divides a multi-port memory element into multiple dual-port memory elements (first bank and second bank), each handling specific port operations. The first dual-port element handles first read port and second write port, while the second dual-port element handles second read port and first write port, enabling concurrent operations across banks while keeping individual elements simple
Solution Approach 2:
The patent combines multiple dual-port memory elements into a unified multi-port memory structure where banks are merged through shared control circuitry and data paths. The control circuitry merges address signals and control signals to coordinate operations across banks, creating a functional multi-port memory that achieves high bandwidth without requiring a single complex multi-port element
2Speed
If dual-port memory elements are used, then resource consumption is reduced, but memory access speed is limited due to single operation support
Solution Approach 1:
The patent segments the memory system into multiple specialized banks where each dual-port memory element is optimized for specific read/write operations. This segmentation allows parallel processing of multiple memory requests simultaneously, increasing overall access speed while using only necessary number of dual-port elements
Solution Approach 2:
The control circuitry performs preliminary routing and addressing of memory requests to appropriate banks before actual data access occurs. By pre-coordinating which bank handles which operation and pre-managing data paths, the system enables immediate concurrent operations without waiting for sequential arbitration, thus increasing access speed
3Productivity
If multiple dual-port memory elements are used to enable concurrent operations, then memory access bandwidth increases, but control circuitry complexity increases
Solution Approach 1:
The control circuitry is designed with multi-functional capabilities to handle addressing, routing, and coordination for multiple banks simultaneously. A single control unit performs multiple functions including address decoding, bank selection, and data path management, reducing the need for separate control logic for each bank and thereby managing complexity while supporting concurrent operations
Solution Approach 2:
The control circuitry acts as an intermediary between multiple dual-port memory elements and the external interface. It mediates incoming memory requests by routing them to appropriate banks, coordinating read/write operations, and managing data flow between banks and ports, thus simplifying the interface complexity while enabling complex concurrent operations across multiple elements
4Adaptability or versatility
If dual-port memory elements are used, then device simplicity is maintained, but multiple read and write requests cannot be performed simultaneously
Solution Approach 1:
The patent segments the memory system into functionally specialized banks where each dual-port element is assigned specific read/write port combinations. This segmentation enables the system to adapt to different operation patterns (simultaneous reads, simultaneous writes, mixed operations) by directing requests to appropriate banks, thereby increasing operational versatility while maintaining simple dual-port element structures
Solution Approach 2:
The memory system employs dynamic bank selection and data path routing controlled by control circuitry that adapts to the type of operation requested. The system dynamically configures which bank handles which operation based on real-time request patterns, enabling versatile concurrent operations while keeping the physical memory element arrangement relatively simple and regular
Data Source
AI summary
Integrated circuits may include memory element circuitry. The memory element circuitry may include multiple dual-port memory elements that are controlled to effectively form a multi-port memory element having multiple read and write ports. A respective bank of dual-port memory elements may be coupled to each write port. Write data may be received concurrently over one or more of the write ports and stored on the banks. Switching circuitry may be coupled between the banks and the read ports of the memory element circuitry. The switching circuitry may be controlled using read control signals generated by logic XOR-based control circuitry. The control circuitry may include dual-port memory elements that store addressing signals associated with the write data. The read control signals may control the switching circuitry to selectively route the most-recently written data to corresponding read ports during a data read operation.