Emulated Stream Clock Signal Generation for Asynchronous Data Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data transmission systems face challenges in maintaining a consistent stream clock frequency across varying data rates, especially in asynchronous links, where the original stream clocking information is lost, and different data sources or vendors may have different frequency ranges, making it difficult to ensure continuous and lossless data transmission.
Innovation Solution
A method and apparatus that generate an emulated stream clock signal using a transmitter and receiver module system, which includes a scheme to estimate and adjust the clock frequency to match the original stream clock frequency, allowing for continuous data transmission over asynchronous links or packet networks without prior knowledge of the exact frequency, with features like frequency estimation, metric-based adjustments, and jitter performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the original stream clocking information is transmitted over an asynchronous link, then data transmission can occur across different data rates, but the stream clocking information is lost and cannot be recovered
Solution Approach 1:
The patent creates a copy of the stream clock signal by generating an emulated clock at the receiver end that matches the original transmitter clock frequency. This copy is achieved through frequency estimation algorithms that analyze the asynchronous data stream and reconstruct the clock characteristics without direct transmission of clock signals.
Solution Approach 2:
The patent introduces an intermediary emulated clock signal that acts as a bridge between the asynchronous transmission medium and the synchronous data reconstruction requirement. This intermediary clock is generated through frequency estimation and serves as the mediator that enables data recovery without direct clock signal transmission.
2Ease of manufacture
If a fixed frequency range is used for stream clock, then system design is simplified, but the system cannot adapt to different data sources with varying frequency ranges
Solution Approach 1:
The patent implements a dynamic frequency estimation mechanism that continuously adapts to the actual stream clock frequency regardless of the data source. The system transitions from static fixed-frequency designs to dynamic frequency detection and adjustment, enabling adaptation to Camera Link (20-85 MHz), DVI (25-165 MHz), and other interface standards.
Solution Approach 2:
The patent changes the operating parameter from fixed frequency to variable frequency estimation. The system monitors and adjusts the emulated clock frequency based on the detected characteristics of the incoming data stream, allowing seamless adaptation to different interface standards and data sources without hardware reconfiguration.
3Reliability
If the emulated clock frequency is adjusted to match the original stream clock, then data transmission becomes continuous and lossless, but the adjustment process introduces complexity in frequency estimation and control
Solution Approach 1:
The patent implements feedback mechanisms where the receiver continuously monitors the data stream and adjusts the emulated clock frequency based on detected timing characteristics. The frequency estimation algorithm provides feedback to the clock generation circuit, creating a closed-loop system that maintains synchronization without direct clock signal transmission.
Solution Approach 2:
The patent replaces direct mechanical/electrical clock signal transmission with software-based frequency estimation and digital clock generation. Instead of physically transmitting the clock signal through cables or circuits, the system uses algorithmic frequency detection and digital synthesis to recreate the clock, reducing physical complexity while maintaining functional reliability.
Data Source
AI summary
A method and apparatus for emulating stream clock signal in asynchronous data transmission. The inventive subject matter proposes a system consisting of a transmitter module, a receiver module, and a link or network in between. A scheme to generate the emulated stream clock across a wide frequency range is also proposed with the property of controllable deviation from the original stream frequency to meet jitter requirement and fast frequency convergence (minimal number of converging steps). The scheme includes an optional first step to derive a frequency estimation of the stream clock and a second step of continuous adjusting the emulated clock frequency to keep the average frequency equals that of the original stream clock.