Emulating Hardware-Accelerated Kernels via RTL Simulation
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Solution Overview
Problem
Developers face challenges in verifying functionality and performance of hardware-accelerated program code without access to hardware acceleration devices or the time for complex implementation processes, which are time-consuming and require synthesis, placement, and routing.
Innovation Solution
A method and system for emulating applications with hardware-accelerated kernels using a processor to compile host program code into a host binary and generate a device program binary implementing a register transfer level (RTL) simulator, allowing execution in a different process, with inter-process communication between the host binary and the RTL simulator through an emulation driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware acceleration devices are used to verify functionality and performance, then accuracy and reliability of verification is improved, but device complexity and cost increase
Solution Approach 1:
The patent creates a software-based RTL simulator that copies the functionality of hardware acceleration devices. The simulator includes a device program binary that implements an RTL simulator using the kernel, allowing developers to verify hardware-accelerated code without needing actual hardware. This copying approach maintains verification accuracy while eliminating the need for complex physical hardware devices.
2Measurement precision
If physical hardware acceleration devices are used for testing, then performance measurement accuracy is improved, but time consumption and accessibility worsen
Solution Approach 1:
The patent replaces the mechanical/physical hardware system with a software-based RTL simulator. The device program binary implements the simulator in software, substituting physical hardware with computational models. This allows performance measurement without the time-consuming processes of synthesis, placement, and routing that are required for actual hardware implementation, while maintaining measurement precision through accurate simulation.
3Ease of manufacture
If hardware implementation processes (synthesis, placement, routing) are completed, then hardware acceleration functionality is achieved, but development time and complexity increase
Solution Approach 1:
The patent performs preliminary action by creating a software simulator before actual hardware implementation. The device program binary and RTL simulator are prepared in advance, allowing developers to verify functionality and perform measurements before committing to the lengthy hardware implementation process. This preliminary software-based verification eliminates the need to complete synthesis, placement, and routing just to test basic functionality.
Data Source
AI summary
Emulating a heterogeneous application having a kernel designated for hardware acceleration may include compiling, using a processor, host program code into a host binary configured to execute in a first process of a computing system and generating, using the processor, a device program binary implementing a register transfer level simulator using the kernel. The device program binary may be configured to execute in a second, different process of the computing system. A high level programming language model of static circuitry of a programmable integrated circuit that couples to a circuit implementation of the kernel may be compiled into a static circuitry binary. The static circuitry binary may be used by the register transfer level simulator during emulation.