Emulation Base Register-Relative Address Conversion
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Solution Overview
Problem
Emulation of programs from older processor systems on newer systems is hindered by the difference in address space sizes, requiring additional instructions to account for wrap-around calculations, which slows down the emulation process.
Innovation Solution
A method that converts base register-relative instructions by determining a projected address on the target processor, allowing for semantically equivalent behavior by using a single additional instruction for each original processor instruction, rather than the typical two, by projecting the sum of the base register and offset onto a cyclical address space and executing the converted instructions with the calculated addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional instructions are inserted to emulate wrap-around calculations for base register-relative addressing, then the correctness of address translation is improved, but the emulation speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating a projected address using a base register and a predetermined offset before the actual address calculation is needed. This projected address is stored and reused for multiple subsequent address calculations, eliminating the need to repeatedly perform wrap-around calculations for multiple instructions that share the same base register, thereby maintaining correctness while improving emulation speed
Solution Approach 2:
The patent merges multiple address calculation operations into a single projected address calculation. By combining the base register value with a predetermined offset once and storing the result, the system avoids performing separate wrap-around calculations for each instruction, reducing the total number of operations required while ensuring correct address translation
2Adaptability or versatility
If two additional instructions are used per original instruction to handle address space differences, then the address space compatibility is improved, but the instruction count and execution time increase
Solution Approach 1:
The patent performs the address space adaptation in advance by calculating a projected address that already accounts for the target processor's address space characteristics. This preliminary calculation stores the adapted address in a register, eliminating the need for repeated adaptation operations and reducing the number of instructions required from two to one per original instruction
Solution Approach 2:
The patent introduces a projected address as an intermediary value between the original processor's address calculation and the target processor's address space. This intermediary stores the pre-adapted address that bridges the two different address spaces, allowing direct use without requiring additional adaptation instructions and reducing execution time
Data Source
AI summary
An original processor uses addresses with a first length of n bits for addressing in a cyclical address space and a target processor uses addresses with a second length of m bits, where the second length m is greater than the first length n. In the original processor, distance values that lie between a lower value min and an upper value max are permissible for the base register-relative addressing. The supported address space on the original processor for the code to be emulated is limited in such a manner that the conversion of address operands as described in the following steps leads to semantically equivalent behavior on the target processor. A projected address on the target processor is initially determined by forming the sum of the content of the base register (R) and an offset (D) that is greater than or equal to a first offset (D1) of a base register-relative instruction and less than the difference (max−min), and projecting the sum onto a cyclical address space with addresses having a length of n bits. Addresses for converting the base register-relative instructions are determined from the calculated projected address and the respective distance values (D1, D2) of the instructions minus the offset D.