Emulation Chip Register Access Optimization
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Solution Overview
Problem
Processor-based hardware emulators face significant bandwidth and latency issues due to high-latency communication channels when updating control registers, particularly in large, high-gate-count integrated circuits, where common methods like read-modify-write or shadow copying lead to inefficient resource usage and coherency problems.
Innovation Solution
A method and apparatus that utilize a communication interface to receive a message with mask and new control bits, read old control bits, operate on them using mask and new control bits to generate updated bits, and write these updated bits back to control registers, optimizing access by using a masking circuit to perform block transfers and manage configuration and trigger bits effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If read-modify-write method is used to change individual bits in a register, then register access is achieved, but communication channel latency and resource usage increase significantly
Solution Approach 1:
The system pre-loads control register values into local shadow memory on the host workstation before actual updates are needed. This preliminary action eliminates the need for repeated read-modify-write cycles over the high-latency communication channel, as the emulator chip can perform updates locally using pre-fetched data.
Solution Approach 2:
The patent implements shadow copies of control registers in local memory on the host workstation. Instead of directly accessing control registers over the communication channel, the system copies register states to local memory, allowing multiple processes to read and modify shadow copies independently, then synchronize changes to the actual registers in bulk, thereby reducing communication latency and channel resource usage.
2Loss of time
If shadow copy of registers is kept in local memory to eliminate multiple transactions, then communication channel usage decreases, but memory usage increases significantly
Solution Approach 1:
The system implements selective shadow copying where only the control register portion that needs to be modified is shadowed in local memory, rather than shadowing the entire register space. This local quality approach minimizes memory usage while still enabling the performance benefits of local updates, as only the necessary shadow copy entries are maintained in host memory.
3Adaptability or versatility
If multiple copies of registers are maintained for multiple processes, then concurrent access is enabled, but coherency problems arise similar to cache coherency issues
Solution Approach 1:
The system implements a feedback mechanism where the emulator chip sends acknowledgment signals back to the host workstation after receiving control register updates. This feedback allows the host to track which processes have successfully updated which registers, enabling the system to manage coherency by knowing the current state of shadow copies and when they need to be synchronized, thereby resolving coherency conflicts between multiple concurrent processes.
Data Source
AI summary
The present patent document relates to a method and apparatus for optimizing access to control registers in an emulation chip. Control messages include in one half of the message a write-mask bits for the corresponding control bits in the other half of the word. A single message from the host workstation can be used to update several bits of the register using a single message, rather than reading, modifying, then writing back each bit individually. Only the bits desired to be updated are written, while the masked bits are not affected. Various configurations of the mask bits and control bits are possible, and block transfers can be used to update bits across a series of registers. The disclosed method and apparatus can reduce overhead and latency on communication channels to the host workstation by significantly reducing the number of individual transfer across the channel.