Emulation System Clock Phase Optimization
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Solution Overview
Problem
Current methods for emulating hardware description models for integrated circuits face limitations in increasing clock frequencies due to signal propagation delays and the need for additional physical connections, which restrict the acceleration of the emulation process and lead to errors in signal detection.
Innovation Solution
Determine signal propagation time delays between semiconductor components and optimize the clock frequency for serialization/deserialization, using a method that involves testing and adjusting the phase shift of the clock signal to ensure correct signal reception across all connections, thereby maximizing the clock frequency and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency for serialization/deserialization is increased to accelerate the emulation process, then the productivity of the emulation system is improved, but signal propagation delays cause errors in signal detection and transmission reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by determining signal propagation delays between semiconductor components before the actual emulation process begins. The system performs delay measurements and clock frequency optimizations in advance, storing these parameters for use during emulation. This allows the system to operate at higher clock frequencies while maintaining signal integrity, as the delay compensation parameters are already established beforehand.
2Reliability
If additional physical connections are provided between FPGAs to reduce signal propagation delays, then the transmission reliability is improved, but the device complexity and number of required connections increases
Solution Approach 1:
The patent applies parameter changes by measuring and compensating for signal propagation delays through clock frequency adjustment and phase shifting rather than adding physical connections. The system modifies temporal parameters (clock frequency, phase shift amounts) to compensate for spatial delays in existing connections. This approach maintains transmission reliability without increasing device complexity or the number of physical connections between FPGAs.
3Reliability
If the phase shift of the clock signal is adjusted to compensate for signal propagation delays, then the signal transmission reliability is improved, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent applies self-service by implementing automatic delay measurement and clock frequency optimization processes that perform themselves without external intervention. The system automatically determines signal propagation delays, calculates optimal clock frequencies and phase shifts, and configures the emulation platform accordingly. This automation reduces the need for complex manual control mechanisms while maintaining high signal transmission reliability.
Data Source
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AI summary
The method involves performing the emulation of the chip design, when a signal transmission between the freely programmable semiconductor components is performed. The signals originating at a first signal transmitting semiconductor component are serialized by a transmitter side timed clock signal, and deserialized by a receiver side timed clock signal on the side. The signal-runtime delays are determined between the semiconductor components and optimize the timing frequency of the clock signal. The runtime delays are determined by considering the emulation of the chip design. Independent claims are included for the following: (1) a method for predicting a maximum operating frequency of a chip design; and (2) a device for performing a method.