Emulation Clock Tree Reduction via Fan-In Cone Pruning
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Solution Overview
Problem
Existing methods for reducing emulation clock tree size in hardware design verification are not aggressive enough and require design-specific patterns, limiting their applicability and effectiveness.
Innovation Solution
A method that identifies and removes fan-in cone sequential elements from the emulation clock tree using formal techniques, such as SystemVerilog Assertions, to determine direct effects and apply pruning techniques for aggressive clock tree reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If topological analysis patterns are used to reduce emulation clock tree size, then clock tree reduction is achieved, but the reduction is not aggressive enough and requires design-specific patterns
Solution Approach 1:
The patent extracts and removes unnecessary sequential elements from the emulation clock tree by identifying fan-in cone sequential elements that do not directly affect the input of sequential elements. This extraction enables aggressive clock tree reduction while maintaining emulation correctness, resolving the contradiction between reducing clock tree size and maintaining emulation frequency.
Solution Approach 2:
The patent employs formal techniques that are universally applicable to different circuit designs without requiring design-specific patterns. The formal method identifies removable sequential elements based on their structural properties and impact analysis, making the clock tree reduction technique universally applicable across various designs while achieving aggressive reduction.
2Quantity of substance
If formal techniques are used to identify fan-in cone sequential elements, then aggressive clock tree reduction is achieved, but the complexity of analysis increases
Solution Approach 1:
The patent segments the analysis process into distinct steps: identifying fan-in cone sequential elements, determining their direct effects on sequential element inputs, and removing unnecessary elements. This segmentation makes the complex formal analysis more manageable and systematic, reducing the perceived complexity while maintaining aggressive reduction capability.
Solution Approach 2:
The patent introduces formal techniques as an intermediary method to bridge the gap between circuit representation and clock tree reduction. This intermediary formalism provides a rigorous yet manageable framework for analyzing sequential element dependencies, making the complex reduction process more controllable and verifiable.
3Productivity
If sequential elements are removed from the clock tree, then emulation frequency improves, but emulation correctness must be maintained
Solution Approach 1:
The patent incorporates feedback mechanisms through formal verification to ensure that removed sequential elements do not compromise emulation correctness. The analysis continuously checks whether the removal of fan-in cone sequential elements maintains the functional equivalence of the emulated circuit, providing confidence in the correctness of the reduced clock tree.
Solution Approach 2:
The patent performs thorough analysis beforehand to identify and remove only those sequential elements that are provably unnecessary. By using formal techniques to verify the impact of removal before actually removing elements, the patent cushions against potential correctness issues and ensures safe reduction.
Data Source
AI summary
The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.