Emulation Compaction Circuit Shared Memory

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Solution Overview

Problem

Existing processor-based emulation systems require large memory footprints due to multiple copies of data for each emulation processor in a cluster, leading to significant power overhead, as most data is not used in subsequent emulation steps.

Innovation Solution

A compaction circuit that stores only data identified by keeptag bits for subsequent reads, dynamically modifying netlists and read addresses to optimize memory usage, allowing for dynamic netlist modification and compaction of emulation data using a shared data array with single-read single-write memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If multiple copies of data are maintained for each emulation processor in a cluster, then read access for multiple processors is enabled, but memory footprint and power consumption increase significantly

Engineering Contradiction:
Improveread accessVSAvoidmemory footprint
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent merges multiple separate memory copies into a single shared memory structure. Instead of maintaining separate data copies for each emulation processor, the system consolidates data into one memory location that can be accessed by multiple processors, thereby reducing overall memory footprint while enabling shared read access.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory structure is designed to serve multiple emulation processors simultaneously. A single memory unit performs the function of multiple separate memory copies by providing read access to multiple processors, making the memory system universal and multi-functional rather than dedicated to individual processors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If multiple copies of data are maintained for each emulation processor in a cluster, then read access for multiple processors is enabled, but power consumption increases significantly

Engineering Contradiction:
Improveread accessVSAvoidpower overhead
Core Design Contradiction:
Ease of operationVSUse of energy by stationary object

Solution Approach 1:

The patent merges multiple separate memory copies into a single shared memory structure. Instead of maintaining separate data copies for each emulation processor, the system consolidates data into one memory location that can be accessed by multiple processors, thereby reducing overall memory footprint while enabling shared read access.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared memory structure is designed to serve multiple emulation processors simultaneously. A single memory unit performs the function of multiple separate memory copies by providing read access to multiple processors, making the memory system universal and multi-functional rather than dedicated to individual processors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If all data is stored in memory for potential future reads, then data availability is ensured, but most stored data is never used

Engineering Contradiction:
Improvedata availabilityVSAvoidpower overhead
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts and stores only the necessary subset of data that will actually be used in subsequent emulation steps. By analyzing which data is required for future operations and storing only that specific portion in memory, the system ensures data availability for needed operations while eliminating the power overhead associated with storing and maintaining unused data.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system dynamically changes the parameter of data selection criteria based on actual usage patterns. By monitoring which data is accessed and adjusting storage decisions accordingly, the system optimizes the balance between data availability and power consumption, storing data selectively rather than universally.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11048843B1Dynamic netlist modification of compacted data arrays in an emulation system
Publication Date: 2021.06.29 CADENCE DESIGN SYST INC
  • US11048843B1 patent drawing
  • US11048843B1 patent drawing
  • US11048843B1 patent drawing

AI summary

A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.