Emulation Control Module for Multi-Core SOC Scan Chain Integrity
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Solution Overview
Problem
In multi-core system-on-chip (SOC) devices, powering down one or more cores during emulation interrupts the serial scan chain, leading to data loss and corruption, preventing data from other cores from exiting or entering the chip.
Innovation Solution
A system comprising a core module, test data shift path, core power control module, and emulation control module, where the emulation control module remains powered on and includes alternative registers to continue data shifting uninterrupted, even when cores are powered down, and communicates with the core power control module to prevent core power changes during emulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a core is powered down during emulation, then power consumption is reduced, but the scan chain is interrupted and emulation capability is lost
Solution Approach 1:
An intermediary register is introduced between the core and the scan chain. When the core is powered down, the intermediary register maintains the connection to the scan chain, allowing data to continue flowing through the system without interruption. This mediator component bridges the gap created by power-down, preserving emulation capability while enabling energy savings.
Solution Approach 2:
The system is segmented into independent power domains, where the core can be powered down independently from the scan chain and intermediary registers. This segmentation allows selective power management - the core consumes less power when not actively computing, while the scan chain and intermediary components remain powered to maintain emulation functionality.
2Use of energy by moving object
If a core is powered down during emulation, then energy is saved, but data from other cores cannot exit the chip
Solution Approach 1:
The scan chain is designed to maintain continuous operation even when individual cores are powered down. The intermediary register ensures that the data flow path remains unbroken, allowing data from other active cores to continue exiting the chip without interruption. This continuous action maintains productivity while enabling energy savings from selective core power-down.
3Use of energy by moving object
If a core is powered down during emulation, then power usage is optimized, but new data cannot flow into the chip
Solution Approach 1:
The intermediary register acts as a mediator that maintains the data input path to the scan chain even when cores are powered down. New data can continue to be shifted into the scan chain through this intermediary component, preserving the system's adaptability and versatility for data input while allowing optimized power usage for the cores.
4Use of energy by moving object
If the scan chain is blocked by a powered-down core, then power is saved, but the entire emulation process is corrupted
Solution Approach 1:
The intermediary register serves as a protective mediator that prevents the power-down state of a core from blocking the scan chain. By maintaining the connection between the core and the scan chain, it ensures data integrity is preserved while still allowing the core to be in a low-power state. This eliminates information loss while maintaining power efficiency.
Solution Approach 2:
The intermediary register is prepared in advance to handle the transition when a core is powered down. It is designed to maintain the scan chain connection proactively, preventing potential data corruption before it can occur. This preliminary preparation ensures data integrity is maintained throughout the power-down transition and subsequent operation.
Data Source
AI summary
A system comprises a multi-core silicon-on-chip (SOC) device. The SOC device includes a core module, a test data shift path, a core power control module, and an emulation control module. The core module includes a TAP controller and a plurality of data registers. The test data shift path is operable to transport data shifted out of one or more of the data registers. The core power control module is operable to control the power status of the core module. The emulation control module includes a plurality of alternative registers operable to shift data into the test data shift path in the event that the core module is powered down by the core power control module such that the shift path continues uninterrupted. The emulation control module remains powered on regardless of the power status of the core module.