Emulation Frame Delta Encoding for IC Verification Data Reduction

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Solution Overview

Problem

Emulation of complex integrated circuits strains computing resources due to the large amount of data required to capture and process signals for timing relationships and digital logic operations, leading to bandwidth and memory limitations, as well as time-intensive data transfer.

Innovation Solution

A method and system that capture a sequence of frames during emulation, including full frames and delta primary frames, which reduce the data captured by focusing on signal changes rather than complete signal states at each clock cycle, allowing for efficient storage and parallel processing to reconstruct waveforms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complete signal states are captured at each clock cycle, then timing relationships and digital logic operations can be verified, but computing resources and bandwidth are excessively strained

Engineering Contradiction:
Improveverification accuracyVSAvoiddata volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential information needed for verification by capturing signal transitions (edges) rather than complete signal states. The delta encoding mechanism extracts only changes from the previous frame, removing redundant data while preserving timing relationships and logic operation information necessary for accurate verification.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of capturing all signal states at every clock cycle (excessive action), the patent captures only signal transitions and changes (partial action). This selective capture approach provides sufficient information for verification without the overhead of complete state recording, reducing data volume while maintaining verification accuracy.

Inventive Principle:
Principle #16Partial or excessive action

2Loss of information

If all signal data is transferred from emulator to analysis system, then complete waveform information is available, but data transfer time and bandwidth requirements increase significantly

Engineering Contradiction:
Improvewaveform information completenessVSAvoiddata transfer time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent changes the representation parameters of signal data by encoding only transitions and changes rather than absolute states. This parameter transformation reduces the amount of information that needs to be transferred while maintaining the ability to reconstruct complete waveform information at the analysis system.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of transferring complete raw signal data, the patent transfers a compressed representation (copy) of the signal information in delta-encoded frame format. This copied representation contains all necessary information for waveform reconstruction but occupies significantly less bandwidth and transfer time.

Inventive Principle:
Principle #26Copying

3Measurement precision

If complete frames are captured for all signals, then all signal states are recorded, but memory requirements and storage burden increase

Engineering Contradiction:
Improvesignal state accuracyVSAvoidmemory requirements
Core Design Contradiction:
Measurement precisionVSVolume of stationary object

Solution Approach 1:

The patent segments the signal capture into full frames and delta frames, where full frames capture complete signal states and delta frames capture only changes. This segmentation allows efficient use of memory by storing only necessary information at each sampling point, reducing overall memory requirements while maintaining signal state accuracy through the combination of full and delta frame data.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11023635B1Sequence of frames generated by emulation and waveform reconstruction using the sequence of frames
Publication Date: 2021.06.01 SYNOPSYS INC
  • US11023635B1 patent drawing
  • US11023635B1 patent drawing
  • US11023635B1 patent drawing

AI summary

An example is a method. A design of an integrated circuit is loaded onto an emulation system and is emulated by the emulation system. A sequence of frames is captured, by the emulation system, from the emulation. The sequence of frames includes frame intervals, and each frame interval includes a full frame and a delta primary frame subsequent to the full frame. The full frame is captured at a respective sample time, and the full frame includes signals of the design or a change of the signals relative to a respective sample time of the full frame of a previous frame interval. The delta primary frame is captured at a respective sample time, and the delta primary frame includes a change of a subset of the signals relative to a respective sample time of a previous frame of the respective frame interval. The sequence of frames is stored to memory.