Emulation-Based Functional Qualification for IC Design Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor design verification methods, particularly for complex SoC devices, face challenges in efficiently isolating and detecting design bugs due to limitations in observability and control, leading to increased time and resource consumption.
Innovation Solution
The implementation of an emulation-based functional qualification system that uses an emulation platform to replace simulation in mutation-based analysis, allowing for the insertion of mutations into integrated circuit designs, parallel setup and activation simulation, and rapid mutant reconfiguration, enabling in-circuit emulation speed for verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If simulation-based verification methods are used for complex SoC devices, then design code coverage can be achieved, but verification time and resource consumption increase significantly
Solution Approach 1:
The patent replaces traditional software-based simulation verification with hardware-based emulation verification. The emulation platform executes verification tests in hardware, providing near-real-time feedback and dramatically reducing verification time from months to days or hours, while maintaining comprehensive code coverage through the same test stimulus generation approaches.
Solution Approach 2:
The patent changes the execution speed parameter from simulation speed (many cycles per second) to emulation speed (real-time or near-real-time operation). This parameter change enables verification to complete in practical timeframes while maintaining the ability to detect design bugs through comprehensive test coverage.
2Speed
If FPGA prototype systems are used for verification, then system execution time is improved, but the ability to isolate root causes of errors is reduced
Solution Approach 1:
The patent introduces an intermediary layer between the FPGA prototype and the verification engineer: a comprehensive logging and traceability system that captures detailed information about signal states, timing relationships, and error conditions. This intermediary enables precise error isolation by recording sufficient detail to trace bugs to their root causes while maintaining fast execution speeds.
Solution Approach 2:
The patent implements enhanced feedback mechanisms that provide detailed information about verification results, including signal waveforms, timing diagrams, and state machine traces. This feedback enables verification engineers to quickly identify and isolate root causes of errors without sacrificing the speed advantages of hardware-based verification.
3Reliability
If verification environments are made more comprehensive to detect all bugs, then detection capability is improved, but complexity of the verification system increases
Solution Approach 1:
The patent segments the verification system into modular components: test stimulus generation, design under test, verification environment, and result analysis. Each component can be independently configured and optimized. This segmentation allows comprehensive bug detection through coordinated operation of multiple specialized modules while managing overall system complexity through clear separation of concerns.
Data Source
AI summary
Techniques for emulation-based functional qualification are disclosed that use an emulation platform to replace simulation in mutation-based analysis. A method for functional qualification of an integrated circuit design includes receiving an integrated circuit design having one or more mutations. Emulation setup and activation simulation are performed in parallel to maximize computing resources. A prototype board can then be programed according to the integrated circuit design and a verification module. A set of test patterns and response generated by a simulation of the integrated circuit using the set of test patterns are stored in a memory of the prototyping board allowing enumeration of mutants to occur at in-circuit emulation speed.