Emulation-Based Logic Circuit Optimization
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Solution Overview
Problem
Current logic circuit design and compilation processes for programmable integrated circuits often result in inefficient performance due to the lack of optimization, as high-level compilation is performed independently of actual device performance, leading to unoptimized configuration data being loaded onto the target device.
Innovation Solution
A logic design system that includes a high-level compiler and an emulation engine to model and monitor the performance of logic circuits, generating emulated profile data to identify optimizations, which are then used to produce optimized HDL descriptions and configuration data for the target device, thereby improving performance without the need for multiple time-consuming HDL compilation operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional independent synthesis is used, then the compilation process is simple and fast, but the performance of the loaded configuration data is unoptimized and inefficient
Solution Approach 1:
The patent applies preliminary action by performing emulation of the logic circuit design before final synthesis and configuration generation. The emulation engine models the target device's behavior in advance, allowing performance profiling and optimization identification to occur prior to actual device programming. This enables the synthesis process to incorporate performance insights without requiring iterative post-loading optimization cycles.
Solution Approach 2:
The patent implements feedback through the emulation engine that profiles the logic circuit's performance and feeds this information back to the synthesis process. The emulation engine generates performance data that influences subsequent synthesis decisions, creating a closed-loop system where synthesis results are evaluated and refined based on actual emulated performance metrics.
2Productivity
If multiple HDL compilation operations are performed to optimize performance, then the performance is improved, but the time required for compilation increases significantly
Solution Approach 1:
The patent uses copying by creating an emulated model of the target device that replicates its behavior without requiring actual hardware or full HDL compilation. The emulation engine creates a virtual representation that can be rapidly instantiated and executed multiple times with different configurations, allowing performance profiling without the time cost of repeated full synthesis operations.
Solution Approach 2:
The patent performs performance profiling and optimization identification in advance through emulation before final configuration generation. By conducting these operations preliminarily on the emulated model, the system avoids the need for multiple time-consuming HDL compilation iterations and can generate optimized configuration data in a single synthesis pass.
3Ease of operation
If configuration data is loaded without performance modeling, then the loading process is fast and simple, but the logic circuit performs inefficiently
Solution Approach 1:
The patent applies preliminary action by completing all performance modeling, profiling, and optimization identification before the actual configuration loading. The emulation engine performs these complex operations in advance on a virtual model, so that when configuration data is ultimately loaded, the system already possesses optimized parameters and insights, allowing simple loading while achieving superior performance.
Data Source
AI summary
Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL. The design system may generate the optimized configuration data without performing multiple, time-consuming, HDL compilations.