Emulation Processor Supporting Four-State Logic
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Solution Overview
Problem
Conventional emulation systems are limited to two-state logic, unable to effectively propagate and model unknown logic signals, leading to potential malfunction or failure in detecting incorrect design behavior in IC designs, as they treat unknown logic signals as known states, which can trigger unintended operations.
Innovation Solution
An emulation processor is configured to support three or four-state logic, including known and unknown states, by leveraging the non-arbitrariness of unknown binary logic signals, allowing it to generate and propagate outputs based on interactions between known and unknown input signals, and model both combinational and sequential operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional emulation systems use two-state logic, then the system complexity is low and operation is simple, but the ability to propagate and model unknown logic signals is lost, leading to malfunction or failure in detecting incorrect design behavior
Solution Approach 1:
The logic state is segmented into two independent components: a known state bit (0 or 1) and an unknown state indicator bit (X or Z). This segmentation allows the system to track both the logical value and the validity status separately, enabling proper propagation of unknown states through logic gates without compromising system operation.
Solution Approach 2:
The emulation system uses composite logic states combining known state information and unknown state information. Each logic signal is represented as a composite entity containing both the binary value and the unknown state flag, allowing the system to model four-state logic (0, 1, X, Z) while maintaining compatibility with existing two-state hardware infrastructure.
2Reliability
If conventional emulation systems treat unknown logic signals as known states, then the system operation is straightforward, but unintended operations are triggered and incorrect design behavior is not detected
Solution Approach 1:
The system implements feedback mechanisms that continuously track the propagation of unknown state indicators through the logic circuit. When an unknown state enters a logic gate, the feedback path updates the output unknown state indicator accordingly, ensuring that downstream components are aware of the indeterminate signal status and can respond appropriately.
Solution Approach 2:
The unknown state indicator acts as an intermediary that mediates between the known logic value and the verification process. This intermediary layer allows the system to carry known state information for normal operation while simultaneously providing verification information to detect incorrect design behavior, without requiring fundamental changes to the operational logic.
3Reliability
If multi-valued signals are fully supported in emulation, then unknown and undriven states can be properly modeled, but the cost overhead increases significantly and system capacity is reduced
Solution Approach 1:
The system implements partial multi-valued logic support by adding only the minimal necessary components (unknown state indicator bits) to achieve four-state logic capability. Rather than fully implementing complex multi-valued logic systems, the invention applies just enough additional logic to propagate unknown states correctly through standard two-state hardware, maintaining high system capacity while achieving the desired verification capability.
Data Source
AI summary
An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.