Asynchronous Transceiver Serial Link for Emulation ICs
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Solution Overview
Problem
Conventional emulation systems face bottlenecks in inter-IC communication due to limited Select I/O capabilities, leading to reduced emulation clock frequencies and increased implementation times as circuit designs grow in size, especially when pin-multiplexing ratios increase.
Innovation Solution
The implementation of a high-speed serial communication system using transceivers with asynchronous transceiver clocks operating at higher frequencies than emulation clocks, enabling multiplexing of multiple nets across ICs with embedded clock signals, and employing edge detectors, framing circuits, scramblers, and physical layer circuits for efficient data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Select I/O is used for inter-IC communication with pin-multiplexing, then the number of nets that can cross IC boundaries is increased, but the emulation clock frequency is reduced
Solution Approach 1:
The patent replaces the mechanical/electrical Select I/O multiplexing system with an optical/high-speed serial transceiver system. The transceivers use differential signaling and high-speed serial communication to transmit multiple nets simultaneously without the frequency degradation caused by time-division multiplexing, thus maintaining high emulation clock frequencies while supporting large numbers of nets.
Solution Approach 2:
The patent changes the communication parameter from low-speed multiplexed Select I/O to high-speed serial transceiver communication. By altering the transmission speed and communication protocol parameters, the system can handle more nets without reducing the emulation clock frequency, as the transceivers operate at higher frequencies independent of the emulation clock.
2Adaptability or versatility
If pin-multiplexing ratio is increased to accommodate more nets, then the capacity to handle circuit design size is improved, but the emulation performance is degraded
Solution Approach 1:
The patent segments the communication function into dedicated transceiver channels, with each transceiver handling multiple nets independently through parallel high-speed serial communication. This segmentation allows the system to scale to larger circuit designs by adding more transceivers without degrading the performance of individual channels, as each operates independently at full speed.
Solution Approach 2:
The transceiver serves multiple functions: it handles data transmission for multiple nets, provides clock signal distribution, and enables high-speed communication across IC boundaries. This multi-functionality allows a single transceiver component to replace what would otherwise require multiple Select I/O pins and complex multiplexing logic, improving both capacity and performance.
3Ease of operation
If Select I/O is used for data transmission, then inter-IC communication is enabled, but the implementation time increases significantly
Solution Approach 1:
The patent performs preliminary configuration of the transceivers and establishes high-speed communication channels before the emulation process begins. The transceivers are pre-programmed with the necessary timing and protocol parameters, allowing data transmission to start immediately without the iterative configuration and tuning required for Select I/O systems, thus reducing implementation time.
4Speed
If the number of Select I/O pins is increased to reduce multiplexing ratio, then the emulation clock frequency is maintained, but the device complexity and cost increase
Solution Approach 1:
The patent merges multiple net transmission functions into a single high-speed serial transceiver channel. Instead of requiring separate physical pins for each net, the transceiver combines multiple data streams into a high-speed serial communication protocol, reducing the number of physical I/O pins and circuit board layers while maintaining high emulation clock frequencies.
Data Source
AI summary
An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.