Emulation Waveform Generation via Selective Signal Tracing
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Solution Overview
Problem
Conventional emulation environments are inefficient in terms of hardware and communication resources when dealing with complex integrated circuits, as they require transferring large amounts of data for analysis, leading to performance issues.
Innovation Solution
The proposed solution involves a host system that configures an emulator to trace and emulate a design under test (DUT), allowing the host system to simulate sections of the DUT to obtain additional signal values, thereby reducing the number of signals that need to be traced by the emulator, which in turn reduces communication bandwidth and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all signals of the DUT are traced by the emulator, then complete emulation results are obtained, but communication bandwidth and hardware resources are excessively consumed
Solution Approach 1:
The patent segments the DUT into multiple sections and selectively traces only those sections that are necessary to obtain the desired signal values. Instead of tracing all signals throughout the entire DUT, the system divides the design into manageable sections and identifies which sections contain the signals of interest, thereby reducing the overall tracing burden and communication bandwidth requirements while maintaining completeness of the required emulation results.
Solution Approach 2:
The patent extracts and identifies only the specific sections of the DUT that contain the signals needed for analysis. By using signal propagation analysis and reachability algorithms, the system extracts the minimal subset of sections that are relevant to the desired signals, excluding all unnecessary sections from the tracing process. This extraction approach ensures that complete information about the required signals is obtained while minimizing communication bandwidth consumption.
2Loss of information
If the emulator traces all signals for multiple cycles, then comprehensive timing relationships are captured, but the data transfer volume becomes extremely large
Solution Approach 1:
The patent segments the time dimension by identifying which signal cycles are actually necessary for capturing timing relationships. Instead of transferring data for all cycles of all signals, the system analyzes timing requirements and segments the emulation data transfer to include only the relevant cycles for the sections that contain timing-critical signals, thereby maintaining comprehensive timing information while reducing overall data transfer volume.
Solution Approach 2:
The patent applies local quality by varying the tracing depth and detail based on the specific characteristics of each section. For sections containing timing-critical signals, the system maintains full-cycle tracing to preserve timing relationships, while for other sections, it reduces or eliminates tracing. This localized approach ensures that timing relationship information is preserved where needed while minimizing data transfer volume overall.
3Measurement precision
If the emulator system processes billions of signals, then accurate verification of complex DUT is achieved, but emulation speed decreases due to resource constraints
Solution Approach 1:
The patent segments the verification process by identifying and focusing computational resources only on the sections of the DUT that contain signals relevant to the verification objectives. By dividing the complex DUT into sections and selectively analyzing only those sections that contribute to verification accuracy, the system maintains measurement precision for the required signals while improving emulation speed by avoiding unnecessary processing of unrelated signals.
Solution Approach 2:
The patent extracts the essential sections needed for accurate verification using reachability analysis and signal propagation algorithms. By removing and excluding unnecessary sections from the verification process, the system achieves the same verification accuracy with significantly reduced computational load, thereby improving emulation speed without sacrificing measurement precision for the critical signals.
Data Source
AI summary
An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.