Emulator Cache Memory Model for SoC Verification Bottlenecks
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Solution Overview
Problem
Modern integrated circuit designs, especially System on Chip (SoC) designs, face significant verification bottlenecks due to the complexity of large memories, which lead to slow simulation times, communication delays, and inefficiencies in memory mapping and data transfer during emulation, requiring more effective memory implementation techniques.
Innovation Solution
The implementation of a memory modeling system using a workstation with a main memory model and a cache memory model in the emulator, where the cache memory is a hardware model and the main memory is a software model, synchronized through an interface optimized for small packets and fast streaming speed, allowing for transparent and efficient data access and minimizing overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large memories are implemented physically on the emulator, then memory capacity is provided, but communication delays and overheads increase
Solution Approach 1:
The memory system is segmented into two parts: a large main memory model stored as a software model on the workstation, and a small cache memory model stored as hardware on the emulator. This segmentation allows the bulk of memory capacity to be provided by the workstation while minimizing communication delays by caching frequently accessed data on the emulator side.
Solution Approach 2:
A cache memory model acts as an intermediary between the emulator and the main memory model. The cache stores a subset of data from the main memory, enabling fast local access for frequently used data while reducing the need for frequent communication with the larger main memory stored on the workstation.
2Speed
If memory is modeled as hardware on the emulator, then access speed is improved, but memory capacity is limited by physical constraints
Solution Approach 1:
The memory system is divided into a hardware cache memory model on the emulator for fast access and a software main memory model on the workstation for large capacity. This allows the emulator to provide fast hardware-based access for frequently accessed data while the workstation provides extensive memory capacity through software modeling.
Solution Approach 2:
A cache memory model is created as a copy of a subset of data from the main memory model. This copy is stored as hardware on the emulator, providing fast access speed while the full main memory model is maintained as software on the workstation for unlimited capacity.
3Speed
If the entire memory is loaded into the emulator, then data access is fast, but memory mapping and data transfer overheads increase
Solution Approach 1:
Only a subset of data from the main memory is extracted and stored in the cache memory model on the emulator. This extraction allows fast data access for frequently used data while avoiding the complexity of mapping and transferring the entire large memory into the emulator.
Solution Approach 2:
Instead of loading the entire memory into the emulator, only a partial subset of data is loaded into the cache. This partial action provides sufficient fast access for typical workloads while significantly reducing memory mapping and data transfer overheads.
Data Source
AI summary
Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.