Emulator Pipeline Reduces I/O Latency via Target Timing Domain Interfacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Emulation systems face latency issues due to round trip cable delay (RTCD) when transferring data between an emulator and a target device, which necessitates longer clock cycles, resulting in slower emulation speeds.
Innovation Solution
Implementing a pipeline approach with a target timing domain interfacing component (TTD) that temporarily stores data across emulation cycles, allowing data transmission at a triggering edge of a subsequent clock cycle to reduce latency and enable shorter, faster clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock cycle is extended to account for RTCD and target device delay, then the emulation system can accommodate the delay, but the emulation speed decreases
Solution Approach 1:
The patent segments the data transfer process into multiple independent clock cycles, separating the RTCD and target device delay from the emulation clock cycle. Data is captured in one cycle and transmitted in a subsequent cycle, allowing the emulation system to use shorter, faster clock cycles while still accommodating the total delay through multiple cycles.
Solution Approach 2:
The patent implements preliminary data capture and storage in a buffer during one clock cycle, before the actual data transmission occurs in a subsequent cycle. This preliminary action allows the system to prepare data in advance, decoupling the capture timing from the transmission timing and enabling faster emulation cycles.
2Productivity
If data is transmitted immediately after capture, then the data flow is continuous, but the RTCD and target device delay cause timing conflicts
Solution Approach 1:
The patent introduces a buffer or storage element as an intermediary between the data capture stage and the data transmission stage. This intermediary component temporarily holds the captured data, allowing the system to manage the timing differences between capture and transmission without losing data or creating timing conflicts.
Solution Approach 2:
Data is preliminarily captured and stored in the buffer during one clock cycle, with the actual transmission occurring in a subsequent cycle. This preliminary capture action separates the data acquisition process from the data transmission process, allowing each to be optimized independently and resolving the timing delay issue.
Data Source
AI summary
Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another embodiment, the emulation system may delay transmitting the input data received at the TTD during the first clock cycle such that that the input data reaches the emulator at a predetermined time during the second clock cycle. As the RTCD is spread across multiple clock cycles, the emulation system may implement faster clocks.