Emulator Speed Controller for Instruction Timing Synchronization
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Solution Overview
Problem
Existing information processing apparatuses face challenges in executing application software developed for different architectures due to compatibility issues, leading to potential deviations in instruction execution timing, especially when a combination of software and hardware emulation is used.
Innovation Solution
An emulator with a speed controller that adjusts emulation speed by intermittently inserting waits into the instruction stream to synchronize the execution timing with the intrinsic speed of the target architecture, using a speed controller comprising an instruction number detector, clock conversion part, comparator, and wait timing controller to fine-tune the insertion frequency of waits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a combination of software and hardware emulation is used to execute application software for a different architecture, then emulation functionality and performance are improved, but execution timing deviates from the intrinsic timing of the target architecture
Solution Approach 1:
The patent implements a feedback mechanism where the emulator monitors the execution timing of instructions and compares it against the intrinsic timing characteristics of the target architecture. Based on this comparison, the emulator dynamically adjusts the timing of instruction execution to match the original architecture's timing behavior, thereby resolving the timing deviation caused by software-hardware combination emulation
Solution Approach 2:
The patent changes the timing parameters of instruction execution within the emulator to match the intrinsic timing characteristics of the target architecture. By adjusting execution speed, timing intervals, and synchronization parameters, the emulator maintains accurate timing relationships despite using a combination of software and hardware emulation approaches
2Reliability
If all devices are emulated by software using a single software clock, then timing synchronization is simplified, but emulation speed and performance are reduced
Solution Approach 1:
The patent segments the emulation system into multiple independent clock domains, with each device or device group having its own dedicated hardware clock. This segmentation allows different parts of the system to operate at optimal speeds independently, improving overall emulation performance while maintaining timing synchronization through coordinated clock management
Solution Approach 2:
The patent implements a multi-functional clock management system that can operate in different modes: single software clock mode for simplified timing, multiple hardware clocks for high performance, and hybrid modes combining both approaches. This universal clock system adapts to different emulation scenarios, providing both synchronization reliability and speed optimization as needed
3Productivity
If multiple devices use different hardware clocks for emulation, then emulation speed is improved, but execution timing becomes inconsistent across devices
Solution Approach 1:
The patent introduces a clock synchronization intermediary that mediates between multiple hardware clocks used by different devices. This intermediary component coordinates the timing relationships between clocks, ensuring that while devices can operate at different speeds for performance optimization, their timing remains consistent and synchronized with the target architecture's timing characteristics
Data Source
AI summary
An emulation technique adjusts the execution timing of instructions included in an application to be emulated. An emulator executes an instruction stream consisting of a plurality of instructions included in the application for an apparatus to be emulated to perform the object AP. This emulator performs successively the instructions included in the instruction stream at a predetermined period, and includes a speed controller for adjusting the emulation speed by intermittently inserting a wait into the instruction stream to emulate execution of the instruction stream. Preferably, this emulator includes a clock generator (145), in which the speed controller counts the clock input from the clock generator (145).