Enable-Gated Latch Clocking for Low-Power Memory Circuits
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Solution Overview
Problem
In electronic devices, latches continue to consume power even when their corresponding functions or circuits are disabled, leading to unnecessary power consumption due to signal passing during disabling periods.
Innovation Solution
An enable signal is used to configure the clock generator to set the clock signal to a 'hold' state when the function or circuit is to be disabled, preventing signal passing and reducing power consumption by using a few logic elements without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the latch continues to operate during disabling periods, then the circuit remains responsive to input signals, but unnecessary power consumption occurs due to signal passing
Solution Approach 1:
The latch circuit dynamically changes its operational state based on the enable signal. When enabled, the latch is in pass mode allowing signal transmission; when disabled, the latch transitions to hold mode maintaining the current output state. This dynamic state change is controlled by the clock signal generation which is gated by the enable signal, allowing the circuit to adapt its behavior to power efficiency requirements while maintaining reliability when needed.
2Ease of operation
If the clock signal continues to toggle during disabling periods, then the latch remains in pass mode, but power consumption increases due to unnecessary signal passing
Solution Approach 1:
The enable signal is processed in advance to determine the operational state of the latch before actual signal processing occurs. The clock generator uses the enable signal to pre-determine whether clock toggling should occur, preventing unnecessary clock transitions and latch signal passing before they can consume power. This preliminary control mechanism ensures that the latch only operates when truly needed.
3Use of energy by moving object
If additional logic elements are added to control the enable signal, then power consumption can be reduced, but chip area increases
Solution Approach 1:
The enable signal serves multiple functions within the latch circuit: it controls the clock generator to determine pass/hold mode, and it directly influences the latch output state. By making the enable signal multi-functional, the circuit achieves power control capabilities without requiring separate dedicated control logic elements, thus reducing the additional chip area that would otherwise be needed.
Solution Approach 2:
The control logic for power management is merged into the existing clock generator and latch structure. The enable signal is integrated into the clock generation logic rather than being a separate control path, and the pass/hold control is combined with the fundamental latch operation. This merging eliminates the need for additional standalone control elements that would increase chip area.
Data Source
AI summary
A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. The latch clock generator includes a first inverter configured to generate an inverted signal of the first enable signal, and a NAND gate coupled to the first inverter to receive the inverted signal of the first enable signal. The NAND gate is configured to generate the latched clock signal based on the clock signal and the inverted signal of the first enable signal.