Enable Vector Data Access Request Format for Non-Contiguous Address Handling
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Solution Overview
Problem
Modern integrated circuits face a bandwidth bottleneck due to increased frequency and number of data access transactions, as existing burst request formats are inefficient in handling non-contiguous address ranges and require complex logic for address conflict detection.
Innovation Solution
The integrated circuit employs a data access request format that includes an enable vector specifying active and inactive portions of a target address range, allowing multiple non-contiguous transactions to be triggered by a single request, reducing the number of requests and simplifying address conflict detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing burst request formats are used to handle data access transactions, then the number of data access transactions can be serviced, but the bandwidth bottleneck increases due to inefficiency in handling non-contiguous address ranges and complex logic requirements for address conflict detection
Solution Approach 1:
The address range is segmented into multiple portions, each associated with an enable indication in the enable vector. This allows the system to efficiently handle non-contiguous address ranges by selectively enabling only the relevant address portions, avoiding the need for complex conflict detection logic while maintaining high transaction handling efficiency.
2Quantity of substance
If the number of data access transactions is increased to meet bandwidth requirements, then the data transfer capacity improves, but the frequency bottleneck worsens due to the increased number of requests and complex processing required
Solution Approach 1:
Multiple data access transactions with non-contiguous address ranges are merged into a single request by using an enable vector to specify multiple active address portions. This combining approach reduces the total number of requests needed, thereby reducing the frequency bottleneck while maintaining the ability to service a large quantity of data access transactions.
Data Source
AI summary
An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.